SAK-TC297TP-96F300N BC

32-Bit Microcontroller TC290 / TC297 / TC298 / TC299 32-Bit Single-Chip Microcontroller BC-Step 32-Bit Single-Chip Microcontroller Data Sheet V 1.0, 2017-03 Microcontrollers Edition 2017-03 Published by Infineon Technologies AG 81726 Munich, Germany © 2017 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com) Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. TC290 / TC297 / TC298 / TC299 BC-Step Revision History Page or Item Subjects (major changes since previous revision) V 1.0, 2017-03 The history is documented in the last chapter Data Sheet 3 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 2.1 2.1.1 2.1.2 2.1.3 2.2 2.2.1 2.2.2 2.2.3 2.3 2.3.1 2.3.2 2.3.3 2.4 2.4.1 2.4.2 2.4.3 Package and Pinning Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TC299x Pin Definition and Functions: BGA516 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TC299x BGA516 Package Variant Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Emergency Stop Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Pull-Up/Pull-Down Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 TC298x Pin Definition and Functions: BGA416 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 TC298x BGA416 Package Variant Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Emergency Stop Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Pull-Up/Pull-Down Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 TC297x Pin Definition and Functions: BGA292 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 TC297x BGA292 Package Variant Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Emergency Stop Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 Pull-Up/Pull-Down Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 TC29x Bare Die Pad Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Pad Openings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 Emergency Stop Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Pull-Up/Pull-Down Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.13.1 3.14 3.14.1 3.14.2 3.14.3 3.14.4 3.15 3.16 3.17 3.18 3.19 3.20 3.21 3.22 3.23 3.24 Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V / 3.3 V switchable Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High performance LVDS Pads (LVDSH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Medium performance LVDS Pads (LVDSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Back-up Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calculating the 1.3 V Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ERAY Phase Locked Loop (ERAY_PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DAP Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ASCLIN SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ASCLIN SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSPI Timings, Master and Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet TOC-1 316 316 317 318 322 325 345 349 350 356 361 362 363 364 369 371 371 373 375 377 379 381 386 387 388 389 391 393 397 401 V 1.0, 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step 3.25 3.26 3.27 3.28 3.28.1 3.28.2 3.28.3 3.28.4 3.29 3.30 3.31 3.32 3.32.1 3.32.2 3.32.3 3.32.4 3.33 3.34 3.35 3.35.1 3.35.2 3.36 QSPI Timings, Master and Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSC Timing 5 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSC Timing 3.3 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ethernet Interface (ETH) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ETH Measurement Reference Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ETH Management Signal Parameters (ETH_MDC, ETH_MDIO) . . . . . . . . . . . . . . . . . . . . . . . . . ETH MII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ETH RMII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-Ray Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HSCT Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inter-IC (I2C) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EBU Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BFCLKO Output Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EBU Asynchronous Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EBU Burst Mode Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EBU Arbitration Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CIF Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Target Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TC290 Carrier Tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4.1 History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 Changes from TC29xBB_v1.1 to TC29xBC_v1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 Data Sheet 2 406 413 418 423 423 424 425 426 427 429 432 435 435 435 439 441 442 448 451 452 452 454 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Trademarks of Infineon Technologies AG AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™, POWERCODE™; PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™. Other Trademarks Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2011-11-11 Data Sheet 3 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Summary of Features 1 Summary of Features The TC29x product family has the following features: • High Performance Microcontroller with three CPU cores • Two 32-bit super-scalar TriCore CPUs (TC1.6P), each having the following features: – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Multiply-accumulate unit able to sustain 2 MAC operations per cycle – up to 300 MHz operation at full temperature range – up to 120 / 240 Kbyte Data Scratch-Pad RAM (DSPR) – up to 32 Kbyte Instruction Scratch-Pad RAM (PSPR) – 16 / 32 Kbyte Instruction Cache (ICACHE) – 8 Kbyte Data Cache (DCACHE) • Lockstepped shadow cores for TC1.6P core 1 • Multiple on-chip memories – All embedded NVM and SRAM are ECC protected – up to 8 Mbyte Program Flash Memory (PFLASH) – up to 768 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation – 32 Kbyte Memory (LMU) – BootROM (BROM) • 128-Channel DMA Controller with safe data transfer • Sophisticated interrupt system (ECC protected) • High performance on-chip bus structure – 64-bit Cross Bar Interconnect (SRI) giving fast parallel access between bus masters, CPUs and memories – 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units – One bus bridge (SFI Bridge) • Safety Management Unit (SMU) handling safety monitor alarms • Memory Test Unit with ECC, Memory Initialization and MBIST functions (MTU) • Hardware I/O Monitor (IOM) for checking of digital I/O • Versatile On-chip Peripheral Units – Four Asynchronous/Synchronous Serial Channels (ASCLIN) with hardware LIN support (V1.3, V2.0, V2.1 and J2602) up to 50 MBaud – Six Queued SPI Interface Channels (QSPI) with master and slave capability up to 50 Mbit/s – High Speed Serial Link (HSSL) for serial inter-processor communication up to 320 Mbit/s – Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external power devices – Two MultiCAN+ Module with 6 CAN nodes and 384 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer – 15 Single Edge Nibble Transmission (SENT) channels for connection to sensors – Up to two FlexRayTM modules with 2 channels (E-Ray) supporting V2.1 – One Generic Timer Module (GTM) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management – One Capture / Compare 6 module (Two kernels CCU60 and CCU61) Data Sheet 4 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Summary of Features • • – One General Purpose 12 Timer Unit (GPT120) – Five channel Peripheral Sensor Interface conforming to V1.3 (PSI5) – Peripheral Sensor Interface with Serial PHY (PSI5-S) – Inter-Integrated Circuit Bus Interface (I2C) conforming to V2.1 – Optional IEEE802.3 Ethernet MAC with RMII and MII interfaces (ETH) Versatile Successive Approximation ADC (VADC) – Cluster of 11 independent ADC kernels – Input voltage range from 0v to 5.5V (ADC supply) Delta-Sigma ADC (DSADC) – Ten channels • Digital programmable I/O ports • On-chip debug support for OCDS Level 1 (CPUs, DMA, On Chip Buses) • Dedicated Emulation Device chip available – multi-core debugging, real time tracing, and calibration – Aurora Gigabit Trace Port (AGBT) on some variants – four/five wire JTAG (IEEE 1149.1) or DAP (Device Access Port) interface • Power Management System and on-chip regulators • Clock Generation Unit with System PLL and Flexray PLL • Embedded Voltage Regulator Data Sheet 5 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Summary of Features Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: • The derivative itself, i.e. its function set, the temperature range, and the supply voltage • The package and the type of delivery. For the available ordering codes for the TC290 / TC297 / TC298 / TC299 please refer to the "AURIX™ TC2x Data Sheet Addendum", which summarizes all available variants. Table 1-1 Overview of TC27x Functions Feature CPU Core TC1.6P Type P Cores / Checker Cores 3/1 300 MHz Max. Freq. FPU yes Program Flash Size 8 Mbyte Data Flash Size 768 Kbyte Cache Instruction (P / E) 16 / 32 / 32 Kbyte 8 Kbyte Data (P / E) SRAM 120 Kbyte / 32 Kbyte 1) Size TC1.6P (DSPR/PSPR) 240Kbyte / 32 Kbyte 240 Kbyte / 32 Kbyte Size LMU 32 Kbyte DMA Channels 128 ADC Channels 72 + 12 Converter 11 DSADC Channels 10 GTM TIM 6 TOM 5 Timer ATOM / MCS 9/6 CMU / ICM 1/1 PSM 2 TBU 1 SPE 4 CMP / MON 1/1 BRC / DPLL 1/1 1 GPT12 2 CCU6 STM Modules 3 FlexRay Modules 2 Channels 4 CAN 6 Nodes 384 Message Objects Data Sheet 2) 6 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Summary of Features Table 1-1 Overview of TC27x Functions (cont’d) Feature QSPI Channels 6 ASCLIN Interfaces 4 I2C Interfaces 2 SENT Channels 15 PSI5 Modules 5 PSI5-S Modules 1 HSSL Channels 1 MSC Channels 3 Ethernet Channels 1 ASIL Level FCE Modules 1 Safety support SMU 1 up to ASIL-D 1 IOM Security 1 HSM Yes ADAS Embedded Voltage Regulator DCDC from 5 V / 3.3 V to 1.3 V Yes Embedded Voltage Regulator LDO from 5 V / 3.3 V to 1.3 V Yes Embedded Voltage Regulator LDO from 5 V to 3.3 V Yes Low Power Feature Standby RAM Yes Packages Type LF-BGA-292-6 / PG-BGA-41626 / PG-LFBGA-516-5 I/O Type 5 V CMOS / 3.3 V CMOS / LVDS Tambient Range −40 … +125°C 1) Address range starts at lowest address defined in the User’s Manual. For reference see the Memory Maps chapter of the User’s Manual. 2) To ensure the processor cores are provided with a constant stream of instructions the Instruction Fetch Units will speculatively fetch instructions from the up to 64 bytes ahead of the current PC. If the current PC is within 64 bytes of the top of an instruction memory the Instruction Fetch Unit may attempt to speculatively fetch instruction from beyond the physical range. This may then lead to error conditions and alarms being triggered by the bus and memory systems. It is therefore recommended that the upper 64 bytes of any memory be unused for instruction storage. Data Sheet 7 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning Definitions 2 Package and Pinning Definitions This chapter gives a pinning of the different packages of the TC290 / TC297 / TC298 / TC299. Data Sheet TOC-8 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: 2.1 TC299x Pin Definition and Functions: BGA516 Figure 2-1 is showing the TC299x Logic Symbol for the package variant: BGA516. 30 29 AK VSS AJ VEXT VSS AH VEBU VEXT AG P25.0 P26.0 28 27 26 VFLEXE P30.15 P30.13 P30.11 P30.14 P30.12 P30.10 25 24 23 22 21 20 19 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 P30.9 P30.7 P30.5 P30.3 P30.1 VFLEXE P31.15 P31.13 P31.11 P31.9 P31.7 P31.5 P31.3 P31.1 VFLEXE VSS VDDM VSSM AN48 AN51 AN53 AN55 NC NC NC P30.8 P30.6 P30.4 P30.2 P30.0 VGATE3P P31.14 P31.12 P31.10 P31.8 P31.6 P31.4 P31.2 P31.0 VFLEXE VSS VDDM VSSM AN49 AN50 AN52 AN54 NC NC NC AJ NC NC AH 18 17 Top-View AF P25.1 P25.2 25 24 23 22 21 20 19 18 17 16 15 14 13 AE P25.3 P25.4 AE VSS P32.3 P32.2 P32.0 P33.13 P33.11 P33.9 P33.7 P33.5 P33.3 P33.1 AN5 AN10 AD P25.5 P25.7 AD VEXT VSS P32.4 VGATE1P P33.12 P33.10 P33.8 P33.6 P33.4 P33.2 P33.0 AN2 AN8 12 11 10 VAGND1 VAREF1 VDDM AN11 AN13 AN16 7 6 AN21 NC AE AN58 AN59 AE AN18 AN19 AN24 AN25 AD AN61 AN60 AD AN26 AN27 AC AN62 AN63 AC AN28 AN29 AB AN64 AN65 AB AA AN66 AN67 AA Y AN69 AN68 Y AN70 W NC P25.8 AC P23.0 VEXT 22 21 20 19 18 17 16 15 14 13 12 11 10 9 P25.10 AB P23.2 P23.1 AB VSS P32.7 P32.6 P33.15 P34.5 P34.3 P34.1 AN1 AN3 AN7 AN9 AN14 AN17 NC AB AA P25.13 P25.12 AA P23.4 P23.3 AA P23.5 VSS P32.5 P33.14 P34.4 P34.2 VEVRSB AN0 AN4 AN6 AN12 AN15 AN22 AN30 AA Y P25.15 P25.14 Y P22.2 P22.3 Y P23.6 P23.7 AN23 AN31 W NC P25.6 W P22.0 P22.1 W P22.5 P22.4 W V NC NC V VDDP3 VDD V P22.7 P22.6 V VDD U P24.1 P24.0 U XTAL1 XTAL2 U P22.9 P22.8 U VSS VSS T P24.3 P24.2 T VSS TRST T P22.11 P22.10 T VSS (AGBT ERR) VSS R NC (VDDPSB ) VSS P VSS VSS R P24.5 P24.4 P P24.7 P24.6 N P24.9 P24.8 R P21.4 P21.2 P P21.5 P21.3 N P20.0 P20.2 R P21.0 TMS P P21.1 TCK N P21.6 P21.7 M P24.11 P24.10 M P20.3 P20.1 M PORST ESR1 L P24.13 P24.12 L P20.8 P20.7 L P20.6 ESR0 K P24.15 P24.14 K P20.11 P20.10 K P20.9 VSS J VEBU VEBU J P20.13 P20.12 J VSS VDDFL3 N VDD VDD 16 15 VSS VSS (AGBT TX0N) VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 14 VSS VSS 13 12 AF 8 P25.9 VSS (AGBT TX0P) AG AN20 P25.11 17 NC AN56 9 AB 18 NC AN57 VSSM AC 19 Y VAGND2 VAREF2 AN35 AN33 W AN34 AN32 W AN37 AN39 W AN71 VDD V AN38 AN36 V AN45 AN44 V NC VSS VSS U AN40 AN41 U AN47 AN46 U P00.14 P00.15 U VSS VSS (AGBT CLKN) T AN42 AN43 T P00.12 P00.11 T P00.13 NC T VSS VSS (AGBT CLKP) R P00.10 P00.8 R P00.9 P00.7 R NC NC R VSS VSS P P01.7 P00.6 P P00.5 P00.4 P P01.14 P01.15 P VDD (VDDSB) N P01.5 P01.6 N P00.3 P00.2 N P01.12 P01.13 N M P00.1 P00.0 M P01.10 P01.11 M L P02.7 P02.8 L P01.9 P01.8 L P01.1 K J VDD VSS VDD VSS VSS VSS VSS VDD (VDDSB) 19 18 17 16 15 14 13 12 VDDFL3 P15.5 P14.2 P12.0 P12.1 P11.0 P11.1 P11.7 P11.8 P11.13 VSS P02.9 K P02.5 P02.6 K P01.2 P15.7 P15.8 P14.7 P14.9 P14.10 P11.4 P11.6 P11.5 P11.14 P11.15 VFLEX VSS J P02.3 P02.4 J P01.0 NC H NC NC M M P01.3 P01.4 P02.10 P02.11 H VSS VSS H P20.14 P15.2 22 21 20 19 18 17 16 15 14 13 12 11 10 9 P02.1 P02.2 G NC NC G P15.0 VSS VDDP3 P15.3 P14.0 P14.4 P14.3 P14.6 P13.0 P13.2 P11.3 P11.10 P11.12 P10.1 P10.4 P10.5 P10.8 VEXT VSS P02.0 G P02.14 P02.15 F VSS VDDP3 P15.1 P15.4 P15.6 P14.1 P14.5 P14.8 P13.1 P13.3 P11.2 P11.9 P11.11 P10.0 P10.3 P10.2 P10.6 P10.7 VEXT NC F P02.12 P02.13 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 F NC NC E NC NC AK V H G F NC NC E D NC NC NC NC D C NC NC NC NC C B VSS VSS A VDDP3 NC NC NC VSS VDDP3 NC NC NC NC 30 29 28 27 26 25 P15.10 P15.12 P15.11 P15.13 24 23 P15.14 NC NC P14.12 P14.14 NC P13.4 P13.6 NC P13.10 P13.12 P13.14 NC NC P10.9 P10.10 NC P10.14 NC VEXT VSS NC B P10.15 NC NC VEXT NC A 5 4 3 2 1 P15.15 NC P14.11 P14.13 P14.15 NC P13.5 P13.7 P13.9 P13.11 P13.13 P13.15 NC NC NC P10.11 P10.13 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 Figure 2-1 TC299x Logic Symbol for the package variant BGA516. Data Sheet TOC-9 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: 2.1.1 TC299x BGA516 Package Variant Pin Configuration Table 2-1 Port 00 Functions Pin Symbol Ctrl Type Function M6 P00.0 I MP / PU1 / VEXT General-purpose input TIN9 CTRAPA GTM input CCU61 input T12HRE CCU60 input INJ00 MSC0 input CIFD9 CIF input P00.0 O0 General-purpose output TOUT9 O1 GTM output ASCLK3 O2 ASCLIN3 output ATX3 O3 ASCLIN3 output – O4 Reserved TXDCAN1 O5 CAN node 1 output – O6 Reserved COUT63 O7 CCU60 output ETHMDIOA HWOU T ETH input/output Data Sheet TOC-10 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 00 Functions (cont’d) Table 2-1 Pin Symbol Ctrl Type Function M7 P00.1 I LP / PU1 / VEXT General-purpose input TIN10 ARX3E N6 GTM input ASCLIN3 input RXDCAN1D CAN node 1 input PSIRX0A PSI5 input SENT0B SENT input CC60INB CCU60 input CC60INA CCU61 input DSCIN5A DSADC channel 5 input DS5NA DSADC positive analog input of channel channel 5, pin A DSCIN7B DSADC channel 7 input VADCG7.5 VADC analog input channel 5 of group 7 CIFD10 CIF input P00.1 O0 General-purpose output TOUT10 O1 GTM output ATX3 O2 ASCLIN3 output – O3 Reserved DSCOUT5 O4 DSADC channel 5 output DSCOUT7 O5 DSADC channel 7 output SPC0 O6 SENT output CC60 O7 CCU61 output P00.2 I TIN11 SENT1B LP / PU1 / VEXT General-purpose input GTM input SENT input DSDIN5A DSADC channel 5 input DSDIN7B DSADC channel 7 input DS5PA DSADC negative analog input of channel 5, pin A VADCG7.4 VADC analog input channel 4 of group 7 CIFD11 CIF input P00.2 O0 General-purpose output TOUT11 O1 GTM output ASCLK3 O2 ASCLIN3 output TXDCANr1 O3 CAN node 1 output (MultiCANr+) PSITX0 O4 PSI5 output TXDCAN3 O5 CAN node 3 output SLSO34 O6 QSPI3 output COUT60 O7 CCU61 output Data Sheet TOC-11 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 00 Functions (cont’d) Table 2-1 Pin Symbol Ctrl Type Function N7 P00.3 I LP / PU1 / VEXT General-purpose input TIN12 RXDCAN3A P6 GTM input CAN node 3 input RXDCANr1A CAN node 1 input (MultiCANr+) PSIRX1A PSI5 input PSISRXA PSI5-S input SENT2B SENT input CC61INB CCU60 input CC61INA CCU61 input DSCIN3A DSADC channel 3 input VADCG7.3 VADC analog input channel 3 of group 7 DSITR5F DSADC channel 5 input CIFD12 CIF input P00.3 O0 General-purpose output TOUT12 O1 GTM output ASLSO3 O2 ASCLIN3 output – O3 Reserved DSCOUT3 O4 DSADC channel 3 output – O5 Reserved SPC2 O6 SENT output CC61 O7 CCU61 output P00.4 I TIN13 REQ7 LP / PU1 / VEXT General-purpose input GTM input SCU input SENT3B SENT input DSDIN3A DSADC channel 3 input DSSGNA DSADC channel input VADCG7.2 VADC analog input channel 2 of group 7 CIFD13 CIF input P00.4 O0 General-purpose output TOUT13 O1 GTM output PSISTX O2 PSI5-S output – O3 Reserved PSITX1 O4 PSI5 output VADCG4BFL0 O5 VADC output SPC3 O6 SENT output COUT61 O7 CCU61 output Data Sheet TOC-12 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 00 Functions (cont’d) Table 2-1 Pin Symbol Ctrl Type Function P7 P00.5 I LP / PU1 / VEXT General-purpose input TIN14 PSIRX2A P9 GTM input PSI5 input SENT4B SENT input CC62INB CCU60 input CC62INA CCU61 input DSCIN2A DSADC channel 2 input VADCG7.1 VADC analog input channel 1 of group 7 CIFD14 CIF input P00.5 O0 General-purpose output TOUT14 O1 GTM output DSCGPWMN O2 DSADC output SLSO33 O3 QSPI3 output DSCOUT2 O4 DSADC channel 2 output VADCG4BFL1 O5 VADC output SPC4 O6 SENT output CC62 O7 CCU61 output P00.6 I TIN15 SENT5B LP / PU1 / VEXT General-purpose input GTM input SENT input DSDIN2A DSADC channel 2 input A VADCG7.0 VADC analog input channel 0 of group 7 (with pull down diagnostics) DSITR4F DSADC channel 4 input F CIFD15 CIF input P00.6 O0 General-purpose output TOUT15 O1 GTM output DSCGPWMP O2 DSADC output VADCG4BFL2 O3 VADC output PSITX2 O4 PSI5 output VADCEMUX10 O5 VADC output SPC5 O6 SENT output COUT62 O7 CCU61 output Data Sheet TOC-13 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 00 Functions (cont’d) Table 2-1 Pin Symbol Ctrl Type Function R6 P00.7 I LP / PU1 / VEXT General-purpose input TIN16 SENT6B R9 GTM input SENT input CC60INC CCU61 input CCPOS0A CCU61 input T12HRB CCU60 input T2INA GPT120 input DSCIN4A DSADC channel 4 input A DS4NA DSADC negative analog input channel 4, pin A VADCG6.5 VADC analog input channel 5 of group 6 CIFCLK CIF input P00.7 O0 General-purpose output TOUT16 O1 GTM output – O2 Reserved VADCG4BFL3 O3 VADC output DSCOUT4 O4 DSADC channel 4 output VADCEMUX11 O5 VADC output SPC6 O6 SENT output CC60 O7 CCU61 output P00.8 I TIN17 SENT7B LP / PU1 / VEXT General-purpose input GTM input SENT input CC61INC CCU61 input CCPOS1A CCU61 input T13HRB CCU60 input T2EUDA GPT120 input DSDIN4A DSADC channel 4 input A DS4PA DSADC positive analog input of channel 4, pin A VADCG6.4 VADC analog input channel 4 of group 6 CIFVSNC CIF input P00.8 O0 General-purpose output TOUT17 O1 GTM output SLSO36 O2 QSPI3 output – O3 Reserved – O4 Reserved VADCEMUX12 O5 VADC output SPC7 O6 SENT output CC61 O7 CCU61 output Data Sheet TOC-14 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 00 Functions (cont’d) Table 2-1 Pin Symbol Ctrl Type Function R7 P00.9 I LP / PU1 / VEXT General-purpose input TIN18 SENT8B R10 GTM input SENT input CC62INC CCU61 input CCPOS2A CCU61 input T13HRC CCU60 input T12HRC CCU60 input T4EUDA GPT120 input DSCIN1A DSADC channel 1 input A VADCG6.3 VADC analog input channel 3 of group 6 DSITR3F DSADC channel 3 input F CIFHSNC CIF input P00.9 O0 General-purpose output TOUT18 O1 GTM output SLSO37 O2 QSPI3 output ARTS3 O3 ASCLIN3 output DSCOUT1 O4 DSADC channel 1 output – O5 Reserved SPC8 O6 SENT output CC62 O7 CCU61 output P00.10 I TIN19 SENT9B LP / PU1 / VEXT General-purpose input GTM input SENT input DSDIN1A DSADC channel 1 input A VADCG6.2 VADC analog input channel 2 of group 6 P00.10 O0 General-purpose output TOUT19 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved SPC9 O6 SENT output COUT63 O7 CCU61 output Data Sheet TOC-15 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 00 Functions (cont’d) Table 2-1 Pin Symbol Ctrl Type Function T6 P00.11 I LP / PU1 / VEXT General-purpose input TIN20 CTRAPA T7 CCU60 input T12HRE CCU61 input DSCIN0A DSADC channel 0 input A VADCG6.1 VADC analog input channel 1 of group 6 P00.11 O0 General-purpose output TOUT20 O1 GTM output – O2 Reserved – O3 Reserved DSCOUT0 O4 DSADC channel 0 output – O5 Reserved – O6 Reserved – O7 Reserved P00.12 I TIN21 ACTS3A T2 GTM input LP / PU1 / VEXT General-purpose input GTM input ASCLIN3 input DSDIN0A DSADC channel 0 input A VADCG6.0 VADC analog input channel 0 of group 6 P00.12 O0 General-purpose output TOUT21 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved COUT63 O7 CCU61 output P00.13 I TIN167 DSDIN6A MP+ / PU1 / VEXT General-purpose input GTM input DSADC channel 6 input A P00.13 O0 General-purpose output TOUT167 O1 GTM output – O2 Reserved – O3 Reserved EXTCLK1 O4 SCU output – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-16 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 00 Functions (cont’d) Table 2-1 Pin Symbol Ctrl Type Function U2 P00.14 I LP / PU1 / VEXT General-purpose input TIN166 DSCIN6A U1 GTM input DSADC channel 6 input A P00.14 O0 General-purpose output TOUT166 O1 GTM output – O2 Reserved – O3 Reserved DSCOUT6 O4 DSADC channel 6 output – O5 Reserved – O6 Reserved – O7 Reserved P00.15 I MP+ / PU1 / VEXT TIN168 DSITR6F General-purpose input GTM input DSADC channel 6 input F P00.15 O0 General-purpose output TOUT168 O1 GTM output – O2 Reserved – O3 Reserved EXTCLK0 O4 SCU output – O5 Reserved – O6 Reserved – O7 Reserved Table 2-2 Port 01 Functions Pin Symbol Ctrl Type Function J2 P01.0 I LP / PU1 / VEXT General-purpose input TIN155 DSITR6E GTM input DSADC channel 6 input E RXDCAN3F CAN node 3 input RXDCANr1E CAN node 1 input (MultiCANr+) P01.0 O0 General-purpose output TOUT155 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-17 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 01 Functions (cont’d) Table 2-2 Pin Symbol Ctrl Type Function K1 P01.1 I LP / PU1 / VEXT General-purpose input TIN159 DSITR8E K2 DSADC channel 8 input E RXD1A1 ERAY1 input SENT10B SENT input P01.1 O0 General-purpose output TOUT159 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P01.2 I TIN156 DSCIN7A M10 GTM input LP / PU1 / VEXT General-purpose input GTM input DSADC channel 7 input A P01.2 O0 General-purpose output TOUT156 O1 GTM output – O2 Reserved TXDCAN3 O3 CAN node 3 output – O4 Reserved TXDCANr1 O5 CAN node 1 output (MultiCANr+) DSCOUT7 O6 DSADC channel 7 output – O7 Reserved P01.3 I TIN111 SLSI3B DSITR7F LP / PU1 / VEXT General-purpose input GTM input QSPI3 input DSADC channel 7 input F P01.3 O0 General-purpose output TOUT111 O1 GTM output – O2 Reserved – O3 Reserved SLSO39 O4 QSPI3 output TXDCAN1 O5 CAN node 1 output – O6 Reserved – O7 Reserved Data Sheet TOC-18 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 01 Functions (cont’d) Table 2-2 Pin Symbol Ctrl Type Function M9 P01.4 I LP / PU1 / VEXT General-purpose input TIN112 RXDCAN1C DSITR7E N10 CAN node 1 input DSADC channel 7 input E P01.4 O0 General-purpose output TOUT112 O1 GTM output – O2 Reserved – O3 Reserved SLSO310 O4 QSPI3 output – O5 Reserved – O6 Reserved – O7 Reserved P01.5 I TIN113 MRST3C LP / PU1 / VEXT DSCIN8A N9 GTM input General-purpose input GTM input QSPI3 input DSADC channel 8 input A P01.5 O0 General-purpose output TOUT113 O1 GTM output – O2 Reserved – O3 Reserved MRST3 O4 QSPI3 output – O5 Reserved DSCOUT8 O6 DSADC channel 8 output – O7 Reserved P01.6 I TIN114 MTSR3C DSDIN8A MP / PU1 / VEXT General-purpose input GTM input QSPI3 input DSADC channel 8 input A P01.6 O0 General-purpose output TOUT114 O1 GTM output – O2 Reserved – O3 Reserved MTSR3 O4 QSPI3 output – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-19 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 01 Functions (cont’d) Table 2-2 Pin Symbol Ctrl Type Function P10 P01.7 I MP / PU1 / VEXT General-purpose input TIN115 SCLK3C DSITR8F L1 GTM input QSPI3 input DSADC channel 8 input F P01.7 O0 General-purpose output TOUT115 O1 GTM output – O2 Reserved – O3 Reserved SCLK3 O4 QSPI3 output – O5 Reserved – O6 Reserved – O7 Reserved P01.8 I TIN162 DSDIN9A LP / PU1 / VEXT General-purpose input GTM input DSADC channel 9 input A SENT12B SENT input ARX0C ASCLIN0 input RXDCAN0F CAN node 0 input RXDCANr0E CAN node 0 input (MultiCANr+) RXD1B1 ERAY1 input P01.8 O0 General-purpose output TOUT162 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-20 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 01 Functions (cont’d) Table 2-2 Pin Symbol Ctrl Type Function L2 P01.9 I LP / PU1 / VEXT General-purpose input TIN160 DSCIN9A SENT11B M2 DSADC channel 9 input A SENT input P01.9 O0 General-purpose output TOUT160 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved DSCOUT9 O6 DSADC channel 9 output – O7 Reserved P01.10 I TIN163 DSITR9F LP / PU1 / VEXT SENT13B M1 GTM input General-purpose input GTM input DSADC channel 9 input F SENT input P01.10 O0 General-purpose output TOUT163 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P01.11 I TIN165 DSITR9E SENT14B LP / PU1 / VEXT General-purpose input GTM input DSADC channel 9 input E SENT input P01.11 O0 General-purpose output TOUT165 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-21 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 01 Functions (cont’d) Table 2-2 Pin Symbol Ctrl Type Function N2 P01.12 I MP+ / PU1 / VEXT General-purpose input TIN158 N1 P01.12 O0 TOUT158 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved TXD1A O6 ERAY1 output – O7 Reserved P01.13 I TIN161 P2 GTM input MP+ / PU1 / VEXT General-purpose output General-purpose input GTM input P01.13 O0 TOUT161 O1 GTM output ATX0 O2 ASCLIN0 output – O3 Reserved TXDCAN0 O4 CAN node 0 output TXDCANr0 O5 CAN node 0 output (MultiCANr+) TXD1B O6 ERAY1 output – O7 Reserved P01.14 I TIN164 MP+ / PU1 / VEXT General-purpose output General-purpose input GTM input P01.14 O0 TOUT164 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved TXEN1A O6 ERAY1 output – O7 Reserved Data Sheet General-purpose output TOC-22 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 01 Functions (cont’d) Table 2-2 Pin Symbol Ctrl Type Function P1 P01.15 I LP / PU1 / VEXT General-purpose input TIN157 DSDIN7A GTM input DSADC channel 7 input A P01.15 O0 General-purpose output TOUT157 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Table 2-3 Port 02 Functions Pin Symbol Ctrl Type Function G6 P02.0 I MP+ / PU1 / VEXT General-purpose input TIN0 REQ6 GTM input SCU input ARX2G ASCLIN2 input CC60INA CCU60 input CC60INB CCU61 input CIFD0 CIF input P02.0 O0 General-purpose output TOUT0 O1 GTM output ATX2 O2 ASCLIN2 output SLSO31 O3 QSPI3 output DSCGPWMN O4 DSADC output TXDCAN0 O5 CAN node 0 output TXD0A O6 ERAY0 output CC60 O7 CCU60 output Data Sheet TOC-23 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 02 Functions (cont’d) Table 2-3 Pin Symbol Ctrl Type H7 P02.1 I LP / PU1 General-purpose input / VEXT GTM input TIN1 H6 Function REQ14 SCU input ARX2B ASCLIN2 input RXDCAN0A CAN node 0 input RXD0A2 ERAY0 input CIFD1 CIF input P02.1 O0 General-purpose output TOUT1 O1 GTM output SLSO47 O2 QSPI4 output SLSO32 O3 QSPI3 output DSCGPWMP O4 DSADC output – O5 Reserved – O6 Reserved COUT60 O7 CCU60 output P02.2 I TIN2 CC61INA MP+ / PU1 / VEXT General-purpose input GTM input CCU60 input CC61INB CCU61 input CIFD2 CIF input P02.2 O0 General-purpose output TOUT2 O1 GTM output ATX1 O2 ASCLIN1 output SLSO33 O3 QSPI3 output PSITX0 O4 PSI5 output TXDCAN2 O5 CAN node 2 output TXD0B O6 ERAY0 output CC61 O7 CCU60 output Data Sheet TOC-24 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 02 Functions (cont’d) Table 2-3 Pin Symbol Ctrl Type Function J7 P02.3 I LP / PU1 / VEXT General-purpose input TIN3 ARX1G J6 GTM input ASCLIN1 input RXDCAN2B CAN node 2 input RXD0B2 ERAY0 input PSIRX0B PSI5 input DSCIN5B DSADC channel 5 input B SDI11 MSC1 input CIFD3 CIF input P02.3 O0 General-purpose output TOUT3 O1 GTM output ASLSO2 O2 ASCLIN2 output SLSO34 O3 QSPI3 output DSCOUT5 O4 DSADC channel 5 output – O5 Reserved – O6 Reserved COUT61 O7 CCU60 output P02.4 I TIN4 SLSI3A MP+ / PU1 / VEXT General-purpose input GTM input QSPI3 input ECTT1 TTCAN input RXDCAN0D CAN node 0 input CC62INA CCU60 input CC62INB CCU61 input DSDIN5B DSADC channel 5 input B SDA0A I2C0 input CIFD4 CIF input P02.4 O0 General-purpose output TOUT4 O1 GTM output ASCLK2 O2 ASCLIN2 output SLSO30 O3 QSPI3 output PSISCLK O4 PSI5-S output SDA0 O5 I2C0 output TXEN0A O6 ERAY0 output CC62 O7 CCU60 output Data Sheet TOC-25 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 02 Functions (cont’d) Table 2-3 Pin Symbol Ctrl Type Function K7 P02.5 I MP+ / PU1 / VEXT General-purpose input TIN5 MRST3A K6 GTM input QSPI3 input ECTT2 TTCAN input PSIRX1B PSI5 input PSISRXB PSI5-S input SENT3C SENT input DSCIN4B DSADC channel 4 input B SCL0A I2C0 input CIFD5 CIF input P02.5 O0 General-purpose output TOUT5 O1 GTM output TXDCAN0 O2 CAN node 0 output MRST3 O3 QSPI3 output DSCOUT4 O4 DSADC channel 4 output SCL0 O5 I2C0 output TXEN0B O6 ERAY0 output COUT62 O7 CCU60 output P02.6 I TIN6 MTSR3A MP / PU1 / VEXT General-purpose input GTM input QSPI3 input SENT2C SENT input CC60INC CCU60 input CCPOS0A CCU60 input T12HRB CCU61 input T3INA GPT120 input CIFD6 CIF input DSDIN4B DSADC channel 4 input B DSITR5E DSADC channel 5 input E P02.6 O0 General-purpose output TOUT6 O1 GTM output PSISTX O2 PSI5-S output MTSR3 O3 QSPI3 output PSITX1 O4 PSI5 output VADCEMUX00 O5 VADC output – O6 Reserved CC60 O7 CCU60 output Data Sheet TOC-26 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 02 Functions (cont’d) Table 2-3 Pin Symbol Ctrl Type Function L7 P02.7 I MP / PU1 / VEXT General-purpose input TIN7 SCLK3A GTM input QSPI3 input PSIRX2B PSI5 input SENT1C SENT input CC61INC CCU60 input CCPOS1A CCU60 input T13HRB CCU61 input T3EUDA GPT120 input CIFD7 CIF input DSCIN3B DSADC channel 3 input B DSITR4E DSADC channel 4 input E P02.7 O0 General-purpose output TOUT7 O1 GTM output – O2 Reserved SCLK3 O3 QSPI3 output DSCOUT3 O4 DSADC channel 3 output VADCEMUX01 O5 VADC output SPC1 O6 SENT output CC61 O7 CCU60 output Data Sheet TOC-27 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 02 Functions (cont’d) Table 2-3 Pin Symbol Ctrl Type L6 P02.8 I SENT0C LP / PU1 General-purpose input / GTM input VEXT SENT input CC62INC CCU60 input CCPOS2A CCU60 input T12HRC CCU61 input T13HRC CCU61 input T4INA GPT120 input CIFD8 CIF input DSDIN3B DSADC channel 3 input B DSITR3E DSADC channel 3 input E TIN8 K9 Function P02.8 O0 General-purpose output TOUT8 O1 GTM output SLSO35 O2 QSPI3 output – O3 Reserved PSITX2 O4 PSI5 output VADCEMUX02 O5 VADC output ETHMDC O6 ETH output CC62 O7 CCU60 output P02.9 I TIN116 LP / PU1 / VEXT General-purpose input GTM input P02.9 O0 TOUT116 O1 GTM output ATX2 O2 ASCLIN2 output – O3 Reserved – O4 Reserved TXDCAN1 O5 CAN node 1 output – O6 Reserved – O7 Reserved Data Sheet General-purpose output TOC-28 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 02 Functions (cont’d) Table 2-3 Pin Symbol Ctrl Type Function L10 P02.10 I LP / PU1 / VEXT General-purpose input TIN117 ARX2C RXDCAN1E L9 ASCLIN2 input CAN node 1 input P02.10 O0 General-purpose output TOUT117 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P02.11 I TIN118 F2 GTM input LP / PU1 / VEXT General-purpose input GTM input P02.11 O0 TOUT118 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P02.12 I TIN151 LP / PU1 / VEXT General-purpose output General-purpose input GTM input P02.12 O0 TOUT151 O1 GTM output SLSO35 O2 QSPI3 output SLSO44 O3 QSPI4 output – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet General-purpose output TOC-29 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 02 Functions (cont’d) Table 2-3 Pin Symbol Ctrl Type Function F1 P02.13 I LP / PU1 / VEXT General-purpose input TIN153 G2 P02.13 O0 TOUT153 O1 GTM output SLSO37 O2 QSPI3 output SLSO46 O3 QSPI4 output TXDCAN0 O4 CAN node 0 output TXDCANr0 O5 CAN node 0 output (MultiCANr+) – O6 Reserved – O7 Reserved P02.14 I TIN154 RXDCAN0H LP / PU1 / VEXT RXDCANr0D G1 GTM input General-purpose output General-purpose input GTM input CAN node 0 input CAN node 0 input (MultiCANr+) P02.14 O0 General-purpose output TOUT154 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P02.15 I TIN152 MP+ / PU1 / VEXT General-purpose input GTM input P02.15 O0 TOUT152 O1 GTM output SLSO36 O2 QSPI3 output SLSO45 O3 QSPI4 output – O4 Reserved – O5 Reserved TXEN1B O6 ERAY1 output – O7 Reserved Data Sheet General-purpose output TOC-30 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-4 Port 10 Functions Pin Symbol Ctrl Type Function F12 P10.0 I LP / PU1 / VEXT General-purpose input TIN102 T6EUDB G12 GPT120 input P10.0 O0 General-purpose output TOUT102 O1 GTM output – O2 Reserved SLSO110 O3 QSPI1 output – O4 Reserved VADCG6BFL0 O5 VADC output – O6 Reserved – O7 Reserved P10.1 I TIN103 MRST1A MP+ / PU1 / VEXT T5EUDB F10 GTM input General-purpose input GTM input QSPI1 input GPT120 input P10.1 O0 General-purpose output TOUT103 O1 GTM output MTSR1 O2 QSPI1 output MRST1 O3 QSPI1 output EN01 O4 MSC0 output VADCG6BFL1 O5 VADC output END03 O6 MSC0 output – O7 Reserved P10.2 I TIN104 SCLK1A MP / PU1 / VEXT General-purpose input GTM input QSPI1 input T6INB GPT120 input REQ2 SCU input RXDCAN2E CAN node 2 input SDI01 MSC0 input P10.2 O0 General-purpose output TOUT104 O1 GTM output – O2 Reserved SCLK1 O3 QSPI1 output EN00 O4 MSC0 output VADCG6BFL2 O5 VADC output END02 O6 MSC0 output – O7 Reserved Data Sheet TOC-31 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 10 Functions (cont’d) Table 2-4 Pin Symbol Ctrl Type Function F11 P10.3 I MP / PU1 / VEXT General-purpose input TIN105 MTSR1A G11 GTM input QSPI1 input REQ3 SCU input T5INB GPT120 input P10.3 O0 General-purpose output TOUT105 O1 GTM output VADCG6BFL3 O2 VADC output MTSR1 O3 QSPI1 output EN00 O4 MSC0 output END02 O5 MSC0 output TXDCAN2 O6 CAN node 2 output – O7 Reserved P10.4 I TIN106 MTSR1C MP+ / PU1 / VEXT General-purpose input GTM input QSPI1 input CCPOS0C CCU60 input T3INB GPT120 input P10.4 O0 General-purpose output TOUT106 O1 GTM output – O2 Reserved SLSO18 O3 QSPI1 output MTSR1 O4 QSPI1 output EN00 O5 MSC0 output END02 O6 MSC0 output – O7 Reserved Data Sheet TOC-32 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 10 Functions (cont’d) Table 2-4 Pin Symbol Ctrl Type Function G10 P10.5 I LP / PU1 / VEXT General-purpose input TIN107 HWCFG4 F9 GTM input SCU input RXDCANr0A CAN node 0 input (MultiCANr+) INJ01 MSC0 input P10.5 O0 General-purpose output TOUT107 O1 GTM output ATX2 O2 ASCLIN2 output SLSO38 O3 QSPI3 output SLSO19 O4 QSPI1 output T6OUT O5 GPT120 output ASLSO2 O6 ASCLIN2 output PSITX3 O7 PSI5 output P10.6 I TIN108 ARX2D LP / PU1 / VEXT General-purpose input GTM input ASCLIN2 input MTSR3B QSPI3 input PSIRX3C PSI5 input HWCFG5 SCU input P10.6 O0 General-purpose output TOUT108 O1 GTM output ASCLK2 O2 ASCLIN2 output MTSR3 O3 QSPI3 output T3OUT O4 GPT120 output TXDCANr0 O5 CAN node 0 output (MultiCANr+) MRST1 O6 QSPI1 output VADCG7BFL0 O7 VADC output Data Sheet TOC-33 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 10 Functions (cont’d) Table 2-4 Pin Symbol Ctrl Type Function F8 P10.7 I LP / PU1 / VEXT General-purpose input TIN109 ACTS2A G9 GTM input ASCLIN2 input MRST3B QSPI3 input REQ4 SCU input CCPOS1C CCU60 input T3EUDB GPT120 input P10.7 O0 General-purpose output TOUT109 O1 GTM output – O2 Reserved MRST3 O3 QSPI3 output VADCG7BFL1 O4 VADC output TXDCANr0 O5 CAN node 0 output (MultiCANr+) – O6 Reserved – O7 Reserved P10.8 I TIN110 SCLK3B LP / PU1 / VEXT General-purpose input GTM input QSPI3 input REQ5 SCU input CCPOS2C CCU60 input T4INB GPT120 input RXDCANr0B CAN node 0 input (MultiCANr+) P10.8 O0 General-purpose output TOUT110 O1 GTM output ARTS2 O2 ASCLIN2 output SCLK3 O3 QSPI3 output – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-34 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 10 Functions (cont’d) Table 2-4 Pin Symbol Ctrl Type Function B8 P10.9 I LP / PU1 / VEXT General-purpose input TIN265 SENT10C B7 SENT input P10.9 O0 General-purpose output TOUT265 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P10.10 I TIN266 SENT11C A7 GTM input LP / PU1 / VEXT General-purpose input GTM input SENT input P10.10 O0 General-purpose output TOUT266 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P10.11 I TIN269 SENT14C LP / PU1 / VEXT General-purpose input GTM input SENT input P10.11 O0 General-purpose output TOUT269 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-35 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 10 Functions (cont’d) Table 2-4 Pin Symbol Ctrl Type Function A6 P10.13 I LP / PU1 / VEXT General-purpose input TIN268 SENT13C B5 SENT input P10.13 O0 General-purpose output TOUT268 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P10.14 I TIN267 SENT12C A5 GTM input LP / PU1 / VEXT General-purpose input GTM input SENT input P10.14 O0 General-purpose output TOUT267 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P10.15 I TIN270 LP / PU1 / VEXT General-purpose input GTM input P10.15 O0 TOUT270 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet General-purpose output TOC-36 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-5 Port 11 Functions Pin Symbol Ctrl Type Function K15 P11.0 I MP+ / PU1 / VFLEX General-purpose input TIN119 ARX3B K14 ASCLIN3 input P11.0 O0 General-purpose output TOUT119 O1 GTM output ATX3 O2 ASCLIN3 output – O3 Reserved – O4 Reserved – O5 Reserved ETHTXD3 O6 ETH output – O7 Reserved P11.1 I TIN120 F15 GTM input MP+ / PU1 / VFLEX General-purpose input GTM input P11.1 O0 TOUT120 O1 GTM output ASCLK3 O2 ASCLIN3 output ATX3 O3 ASCLIN3 output – O4 Reserved – O5 Reserved ETHTXD2 O6 ETH output – O7 Reserved P11.2 I TIN95 MPR/ PU1 / VFLEX General-purpose output General-purpose input GTM input P11.2 O0 TOUT95 O1 GTM output END03 O2 MSC0 output SLSO05 O3 QSPI0 output SLSO15 O4 QSPI1 output EN01 O5 MSC0 output ETHTXD1 O6 ETH output COUT63 O7 CCU60 output Data Sheet General-purpose output TOC-37 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 11 Functions (cont’d) Table 2-5 Pin Symbol Ctrl Type Function G15 P11.3 I MPR / PU1 / VFLEX General-purpose input TIN96 MRST1B SDI03 J15 QSPI1 input MSC0 input P11.3 O0 General-purpose output TOUT96 O1 GTM output – O2 Reserved MRST1 O3 QSPI1 output TXD0A O4 ERAY0 output – O5 Reserved ETHTXD0 O6 ETH output COUT62 O7 CCU60 output P11.4 I TIN121 ETHRXCLKB J13 GTM input MP+ / PU1 / VFLEX General-purpose input GTM input ETH input P11.4 O0 General-purpose output TOUT121 O1 GTM output ASCLK3 O2 ASCLIN3 output – O3 Reserved – O4 Reserved – O5 Reserved ETHTXER O6 ETH output – O7 Reserved P11.5 I TIN122 ETHTXCLKA LP / PU1 / VFLEX General-purpose input GTM input ETH input P11.5 O0 General-purpose output TOUT122 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-38 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 11 Functions (cont’d) Table 2-5 Pin Symbol Ctrl Type Function J14 P11.6 I MPR / PU1 / VFLEX General-purpose input TIN97 SCLK1B K13 QSPI1 input P11.6 O0 General-purpose output TOUT97 O1 GTM output TXEN0B O2 ERAY0 output SCLK1 O3 QSPI1 output TXEN0A O4 ERAY0 output FCLP0 O5 MSC0 output ETHTXEN O6 ETH output COUT61 O7 CCU60 output P11.7 I TIN123 ETHRXD3 K12 GTM input LP / PU1 / VFLEX General-purpose input GTM input ETH input P11.7 O0 General-purpose output TOUT123 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P11.8 I TIN124 ETHRXD2 LP / PU1 / VFLEX General-purpose input GTM input ETH input P11.8 O0 General-purpose output TOUT124 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-39 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 11 Functions (cont’d) Table 2-5 Pin Symbol Ctrl Type Function F14 P11.9 I MP+ / PU1 / VFLEX General-purpose input TIN98 MTSR1B G14 GTM input QSPI1 input RXD0A1 ERAY0 input ETHRXD1 ETH input P11.9 O0 General-purpose output TOUT98 O1 GTM output – O2 Reserved MTSR1 O3 QSPI1 output – O4 Reserved SOP0 O5 MSC0 output – O6 Reserved COUT60 O7 CCU60 output P11.10 I TIN99 REQ12 LP / PU1 / VFLEX General-purpose input GTM input SCU input ARX1E ASCLIN1 input SLSI1A QSPI1 input RXDCAN3D CAN node 3 input RXD0B1 ERAY0 input ETHRXD0 ETH input SDI00 MSC0 input P11.10 O0 General-purpose output TOUT99 O1 GTM output – O2 Reserved SLSO03 O3 QSPI0 output SLSO13 O4 QSPI1 output – O5 Reserved – O6 Reserved CC62 O7 CCU60 output Data Sheet TOC-40 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 11 Functions (cont’d) Table 2-5 Pin Symbol Ctrl Type Function F13 P11.11 I MP+ / PU1 / VFLEX General-purpose input TIN100 ETHCRSDVA G13 GTM input ETH input ETHRXDVA ETH input ETHCRSB ETH input P11.11 O0 General-purpose output TOUT100 O1 GTM output END02 O2 MSC0 output SLSO04 O3 QSPI0 output SLSO14 O4 QSPI1 output EN00 O5 MSC0 output TXEN0B O6 ERAY0 output CC61 O7 CCU60 output P11.12 I TIN101 ETHREFCLK MPR / PU1 / VFLEX General-purpose input GTM input ETH input ETHTXCLKB ETH input (Not for productive purposes) ETHRXCLKA ETH input (Not for productive purposes) P11.12 O0 General-purpose output TOUT101 O1 GTM output ATX1 O2 ASCLIN1 output GTMCLK2 O3 GTM output TXD0B O4 ERAY0 output TXDCAN3 O5 CAN node 3 output EXTCLK1 O6 SCU output CC60 O7 CCU60 output Data Sheet TOC-41 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 11 Functions (cont’d) Table 2-5 Pin Symbol Ctrl Type Function K11 P11.13 I LP / PU1 / VFLEX General-purpose input TIN125 ETHRXERA SDA1A J12 ETH input I2C1 input P11.13 O0 General-purpose output TOUT125 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved SDA1 O6 I2C1 output – O7 Reserved P11.14 I TIN126 ETHCRSDVB J11 GTM input LP / PU1 / VFLEX General-purpose input GTM input ETH input ETHRXDVB ETH input ETHCRSA ETH input SCL1A I2C1 input P11.14 O0 General-purpose output TOUT126 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved SCL1 O6 I2C1 output – O7 Reserved P11.15 I TIN127 ETHCOL LP / PU1 / VFLEX General-purpose input GTM input ETH input P11.15 O0 General-purpose output TOUT127 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-42 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-6 Port 12 Functions Pin Symbol Ctrl Type Function K17 P12.0 I LP / PU1 / VFLEX General-purpose input TIN128 ETHRXCLKC RXDCAN0C GTM input ETH input CAN node 0 input P12.0 O0 General-purpose output TOUT128 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved ETHMDC O6 ETH output – O7 Reserved P12.1 K16 I TIN129 LP / PU1 / VFLEX General-purpose input GTM input P12.1 O0 General-purpose output TOUT129 O1 GTM output ASLSO3 O2 ASCLIN3 output – O3 Reserved – O4 Reserved TXDCAN0 O5 CAN node 0 output – O6 Reserved – O7 Reserved ETHMDIOC HWOU T ETH input/output Table 2-7 Port 13 Functions Pin Symbol Ctrl Type Function G17 P13.0 I LVDSM_N / PU1 / VEXT General-purpose input TIN91 GTM input P13.0 O0 TOUT91 O1 GTM output END03 O2 MSC0 output SCLK2N O3 QSPI2 output (LVDS) EN01 O4 MSC0 output FCLN0 O5 MSC0 output (LVDS) FCLND0 O6 MSC0 output (LVDS) – O7 Reserved Data Sheet TOC-43 General-purpose output V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-7 Port 13 Functions (cont’d) Pin Symbol Ctrl Type Function F17 P13.1 I LVDSM_P / PU1 / VEXT General-purpose input TIN92 SCL0B GTM input I2C0 input P13.1 O0 General-purpose output TOUT92 O1 GTM output – O2 Reserved SCLK2P O3 QSPI2 output (LVDS) – O4 Reserved FCLP0 O5 MSC0 output (LVDS) SCL0 O6 I2C0 output – O7 Reserved P13.2 G16 I TIN93 CAPINA LVDSM_N / PU1 / VEXT SDA0B General-purpose input GTM input GPT120 input I2C0 input P13.2 O0 General-purpose output TOUT93 O1 GTM output – O2 Reserved MTSR2N O3 QSPI2 output (LVDS) FCLP0 O4 MSC0 output SON0 O5 MSC0 output (LVDS) SDA0 O6 I2C0 output SOND0 O7 MSC0 output (LVDS) P13.3 F16 I TIN94 LVDSM_P / PU1 / VEXT General-purpose input GTM input P13.3 O0 TOUT94 O1 GTM output – O2 Reserved MTSR2P O3 QSPI2 output (LVDS) – O4 Reserved SOP0 O5 MSC0 output (LVDS) – O6 Reserved – O7 Reserved Data Sheet TOC-44 General-purpose output V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-7 Port 13 Functions (cont’d) Pin Symbol Ctrl Type Function B16 P13.4 I LVDSM_N / PU1 / VEXT General-purpose input TIN253 PSIRX4A GTM input PSI5 input P13.4 O0 General-purpose output TOUT253 O1 GTM output END22 O2 MSC2 output – O3 Reserved EN20 O4 MSC2 output FCLN2 O5 MSC2 output (LVDS) FCLND2 O6 MSC2 output (LVDS) – O7 Reserved P13.5 A16 I TIN254 LVDSM_P / PU1 / VEXT General-purpose input GTM input P13.5 O0 TOUT254 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved FCLP2 O5 MSC2 output (LVDS) – O6 Reserved – O7 Reserved P13.6 B15 I TIN255 LVDSM_N / PU1 / VEXT General-purpose output General-purpose input GTM input P13.6 O0 TOUT255 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved SON2 O5 MSC2 output (LVDS) SOND2 O6 MSC2 output (LVDS) – O7 Reserved Data Sheet TOC-45 General-purpose output V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-7 Port 13 Functions (cont’d) Pin Symbol Ctrl Type Function A15 P13.7 I LVDSM_P / PU1 / VEXT General-purpose input TIN256 GTM input P13.7 O0 TOUT256 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved SOP2 O5 MSC2 output (LVDS) – O6 Reserved – O7 Reserved P13.9 A14 I TIN248 SCL1B MP / PU1 / VEXT General-purpose output General-purpose input GTM input I2C1 input P13.9 O0 General-purpose output TOUT248 O1 GTM output ATX3 O2 ASCLIN3 output SLSO55 O3 QSPI5 output – O4 Reserved TXDCANr1 O5 CAN node 1 output (MultiCANr+) SCL1 O6 I2C1 output – O7 Reserved P13.10 B13 I TIN251 PSIRX3A LP / PU1 / VEXT General-purpose input GTM input PSI5 input P13.10 O0 General-purpose output TOUT251 O1 GTM output ATX0 O2 ASCLIN0 output – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-46 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-7 Port 13 Functions (cont’d) Pin Symbol Ctrl Type Function A13 P13.11 I LP / PU1 / VEXT General-purpose input TIN250 ARX0E GTM input ASCLIN0 input P13.11 O0 General-purpose output TOUT250 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved PSITX3 O5 PSI5 output – O6 Reserved – O7 Reserved P13.12 B12 I TIN249 ARX3H LP / PU1 / VEXT General-purpose input GTM input ASCLIN3 input RXDCANr1B CAN node 1 input (MultiCANr+) SDA1B I2C1 input P13.12 O0 General-purpose output TOUT249 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved SDA1 O6 I2C1 output – O7 Reserved P13.13 A12 I TIN262 PSIRX3B LP / PU1 / VEXT INJ20 General-purpose input GTM input PSI5 input MSC2 input P13.13 O0 General-purpose output TOUT262 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-47 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-7 Port 13 Functions (cont’d) Pin Symbol Ctrl Type Function B11 P13.14 I LP / PU1 / VEXT General-purpose input TIN252 GTM input P13.14 O0 TOUT252 O1 GTM output – O2 Reserved SLSO54 O3 QSPI5 output – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P13.15 A11 I TIN264 General-purpose output General-purpose input LP / PU1 / VEXT GTM input P13.15 O0 TOUT264 O1 GTM output – O2 Reserved – O3 Reserved PSITX3 O4 PSI5 output – O5 Reserved – O6 Reserved – O7 Reserved Table 2-8 General-purpose output Port 14 Functions Pin Symbol Ctrl Type Function G21 P14.0 I MP+ / PU1 / VEXT General-purpose input TIN80 SENT12D GTM input SENT input P14.0 O0 General-purpose output TOUT80 O1 GTM output ATX0 O2 ASCLIN0 output Recommended as Boot loader pin TXD0A O3 ERAY0 output TXD0B O4 ERAY0 output TXDCAN1 O5 CAN node 1 output Used for single pin DAP (SPD) function ASCLK0 O6 ASCLIN0 output COUT62 O7 CCU60 output Data Sheet TOC-48 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 14 Functions (cont’d) Table 2-8 Pin Symbol Ctrl Type Function F20 P14.1 I MP / PU1 / VEXT General-purpose input TIN81 REQ15 GTM input SCU input SENT13D SENT input ARX0A ASCLIN0 input Recommended as Boot loader pin RXDCAN1B CAN node 1 input Used for single pin DAP (SPD) function RXD0A3 ERAY0 input RXD0B3 ERAY0 input EVRWUPA SCU input P14.1 O0 General-purpose output TOUT81 O1 GTM output ATX0 O2 ASCLIN0 output Recommended as Boot loader pin. – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved COUT63 O7 CCU60 output P14.2 K18 I TIN82 HWCFG2 EVR13 LP / PU1 / VEXT General-purpose input GTM input SCU input Latched at cold power on reset to decide EVR13 activation. P14.2 O0 General-purpose output TOUT82 O1 GTM output ATX2 O2 ASCLIN2 output SLSO21 O3 QSPI2 output – O4 Reserved – O5 Reserved ASCLK2 O6 ASCLIN2 output – O7 Reserved Data Sheet TOC-49 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 14 Functions (cont’d) Table 2-8 Pin Symbol Ctrl Type Function G19 P14.3 I LP / PU1 / VEXT General-purpose input TIN83 ARX2A GTM input ASCLIN2 input REQ10 SCU input HWCFG3_BMI SCU input SDI02 MSC0 input P14.3 O0 General-purpose output TOUT83 O1 GTM output ATX2 O2 ASCLIN2 output SLSO23 O3 QSPI2 output ASLSO1 O4 ASCLIN1 output ASLSO3 O5 ASCLIN3 output – O6 Reserved – O7 Reserved P14.4 G20 I TIN84 HWCFG6 LP / PU1 / VEXT General-purpose input GTM input SCU input Latched at cold power on reset to decide default pad reset state (PU or HighZ). P14.4 O0 General-purpose output TOUT84 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-50 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 14 Functions (cont’d) Table 2-8 Pin Symbol Ctrl Type Function F19 P14.5 I MP+ / PU1 / VEXT General-purpose input TIN85 HWCFG1 EVR33 GTM input SCU input Latched at cold power on reset to decide EVR33 activation. P14.5 O0 General-purpose output TOUT85 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved TXD0B O6 ERAY0 output TXD1B O7 ERAY1 output P14.6 G18 I TIN86 HWCFG0 DCLDO MP+ / PU1 / VEXT General-purpose input GTM input SCU input If EVR13 active, latched at cold power on reset to decide between LDO and SMPS mode. P14.6 O0 General-purpose output TOUT86 O1 GTM output – O2 Reserved SLSO22 O3 QSPI2 output – O4 Reserved – O5 Reserved TXEN0B O6 ERAY0 output TXEN1B O7 ERAY1 output P14.7 J18 I TIN87 RXD0B0 RXD1B0 LP / PU1 / VEXT General-purpose input GTM input ERAY0 input ERAY1 input P14.7 O0 General-purpose output TOUT87 O1 GTM output ARTS0 O2 ASCLIN0 output SLSO24 O3 QSPI2 output – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-51 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 14 Functions (cont’d) Table 2-8 Pin Symbol Ctrl Type Function F18 P14.8 I LP / PU1 / VEXT General-purpose input TIN88 ARX1D GTM input ASCLIN1 input RXDCAN2D CAN node 2 input RXD0A0 ERAY0 input RXD1A0 ERAY1 input P14.8 O0 General-purpose output TOUT88 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P14.9 J17 I TIN89 ACTS0A MP+ / PU1 / VEXT General-purpose input GTM input ASCLIN0 input P14.9 O0 General-purpose output TOUT89 O1 GTM output END03 O2 MSC0 output EN01 O3 MSC0 output – O4 Reserved TXEN0B O5 ERAY0 output TXEN0A O6 ERAY0 output TXEN1A O7 ERAY1 output P14.10 J16 I TIN90 MP+ / PU1 / VEXT General-purpose input GTM input P14.10 O0 TOUT90 O1 GTM output END02 O2 MSC0 output EN00 O3 MSC0 output ATX1 O4 ASCLIN1 output TXDCAN2 O5 CAN node 2 output TXD0A O6 ERAY0 output TXD1A O7 ERAY1 output Data Sheet General-purpose output TOC-52 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 14 Functions (cont’d) Table 2-8 Pin Symbol Ctrl Type Function A20 P14.11 I LP / PU1 / VEXT General-purpose input TIN258 GTM input P14.11 O0 TOUT258 O1 GTM output END20 O2 MSC2 output PSITX4 O3 PSI5 output EN22 O4 MSC2 output SOP2 O5 MSC2 output – O6 Reserved – O7 Reserved P14.12 B19 I TIN261 SDI20 LP / PU1 / VEXT General-purpose output General-purpose input GTM input MSC2 input P14.12 O0 General-purpose output TOUT261 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P14.13 A19 I TIN260 MP+ / PU1 / VEXT General-purpose input GTM input P14.13 O0 TOUT260 O1 GTM output END23 O2 MSC2 output – O3 Reserved EN21 O4 MSC2 output – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet General-purpose output TOC-53 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 14 Functions (cont’d) Table 2-8 Pin Symbol Ctrl Type Function B18 P14.14 I MP+ / PU1 / VEXT General-purpose input TIN259 GTM input P14.14 O0 TOUT259 O1 GTM output END22 O2 MSC2 output – O3 Reserved EN20 O4 MSC2 output – O5 Reserved – O6 Reserved – O7 Reserved P14.15 A18 I TIN263 INJ21 LP / PU1 / VEXT General-purpose output General-purpose input GTM input MSC2 output P14.15 O0 General-purpose output TOUT263 O1 GTM output ATX1 O2 ASCLIN1 output – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Table 2-9 Port 15 Functions Pin Symbol Ctrl Type Function G25 P15.0 I LP / PU1 / VEXT General-purpose input TIN71 GTM input P15.0 O0 TOUT71 O1 GTM output ATX1 O2 ASCLIN1 output SLSO013 O3 QSPI0 output – O4 Reserved TXDCAN2 O5 CAN node 2 output ASCLK1 O6 ASCLIN1 output – O7 Reserved Data Sheet General-purpose output TOC-54 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 15 Functions (cont’d) Table 2-9 Pin Symbol Ctrl Type Function F23 P15.1 I LP / PU1 / VEXT General-purpose input TIN72 REQ16 H24 GTM input SCU input ARX1A ASCLIN1 input RXDCAN2A CAN node 2 input SLSI2B QSPI2 input EVRWUPB SCU input P15.1 O0 General-purpose output TOUT72 O1 GTM output ATX1 O2 ASCLIN1 output SLSO25 O3 QSPI2 output – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P15.2 I TIN73 SLSI2A MP / PU1 / VEXT General-purpose input GTM input QSPI2 input MRST2E QSPI2 input SENT10D SENT input HSIC2INA QSPI2 input P15.2 O0 General-purpose output TOUT73 O1 GTM output ATX0 O2 ASCLIN0 output SLSO20 O3 QSPI2 output – O4 Reserved TXDCAN1 O5 CAN node 1 output ASCLK0 O6 ASCLIN0 output – O7 Reserved Data Sheet TOC-55 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 15 Functions (cont’d) Table 2-9 Pin Symbol Ctrl Type Function G22 P15.3 I MP / PU1 / VEXT General-purpose input TIN74 ARX0B F22 GTM input ASCLIN0 input SCLK2A QSPI2 input RXDCAN1A CAN node 1 input HSIC2INB QSPI2 input P15.3 O0 General-purpose output TOUT74 O1 GTM output ATX0 O2 ASCLIN0 output SCLK2 O3 QSPI2 output END03 O4 MSC0 output EN01 O5 MSC0 output – O6 Reserved – O7 Reserved P15.4 I TIN75 MRST2A MP / PU1 / VEXT General-purpose input GTM input QSPI2 input REQ0 SCU input SCL0C I2C0 input SENT11D SENT input P15.4 O0 General-purpose output TOUT75 O1 GTM output ATX1 O2 ASCLIN1 output MRST2 O3 QSPI2 output – O4 Reserved – O5 Reserved SCL0 O6 I2C0 output CC62 O7 CCU60 output Data Sheet TOC-56 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 15 Functions (cont’d) Table 2-9 Pin Symbol Ctrl Type Function K19 P15.5 I MP / PU1 / VEXT General-purpose input TIN76 ARX1B F21 ASCLIN1 input MTSR2A QSPI2 input REQ13 SCU input SDA0C I2C0 input P15.5 O0 General-purpose output TOUT76 O1 GTM output ATX1 O2 ASCLIN1 output MTSR2 O3 QSPI2 output END02 O4 MSC0 output EN00 O5 MSC0 output SDA0 O6 I2C0 output CC61 O7 CCU60 output P15.6 I TIN77 MTSR2B J20 GTM input MP / PU1 / VEXT General-purpose input GTM input QSPI2 input P15.6 O0 General-purpose output TOUT77 O1 GTM output ATX3 O2 ASCLIN3 output MTSR2 O3 QSPI2 output SLSO53 O4 QSPI5 output SCLK2 O5 QSPI2 output ASCLK3 O6 ASCLIN3 output CC60 O7 CCU60 output P15.7 I TIN78 ARX3A MRST2B MP / PU1 / VEXT General-purpose input GTM input ASCLIN3 input QSPI2 input P15.7 O0 General-purpose output TOUT78 O1 GTM output ATX3 O2 ASCLIN3 output MRST2 O3 QSPI2 output – O4 Reserved – O5 Reserved – O6 Reserved COUT60 O7 CCU60 output Data Sheet TOC-57 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 15 Functions (cont’d) Table 2-9 Pin Symbol Ctrl Type Function J19 P15.8 I MP / PU1 / VEXT General-purpose input TIN79 SCLK2B REQ1 B24 QSPI2 input SCU input P15.8 O0 General-purpose output TOUT79 O1 GTM output – O2 Reserved SCLK2 O3 QSPI2 output – O4 Reserved – O5 Reserved ASCLK3 O6 ASCLIN3 output COUT61 O7 CCU60 output P15.10 I TIN242 MRST5A A24 GTM input LP / PU1 / VEXT General-purpose input GTM input QSPI5 input P15.10 O0 General-purpose output TOUT242 O1 GTM output – O2 Reserved MRST5 O3 QSPI5 output – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P15.11 I TIN243 SLSI5A LP / PU1 / VEXT General-purpose input GTM input QSPI5 input P15.11 O0 General-purpose output TOUT243 O1 GTM output – O2 Reserved SLSO52 O3 QSPI5 output – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-58 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 15 Functions (cont’d) Table 2-9 Pin Symbol Ctrl Type Function B23 P15.12 I LP / PU1 / VEXT General-purpose input TIN244 A23 P15.12 O0 TOUT244 O1 GTM output – O2 Reserved SLSO51 O3 QSPI5 output – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P15.13 I TIN245 B22 GTM input LP / PU1 / VEXT General-purpose output General-purpose input GTM input P15.13 O0 TOUT245 O1 GTM output – O2 Reserved SLSO50 O3 QSPI5 output – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P15.14 I TIN246 MTSR5A MP / PU1 / VEXT General-purpose output General-purpose input GTM input QSPI5 input P15.14 O0 General-purpose output TOUT246 O1 GTM output – O2 Reserved MTSR5 O3 QSPI5 output – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-59 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Port 15 Functions (cont’d) Table 2-9 Pin Symbol Ctrl Type Function A22 P15.15 I MP / PU1 / VEXT General-purpose input TIN247 SCLK5A GTM input QSPI5 input P15.15 O0 General-purpose output TOUT247 O1 GTM output – O2 Reserved SCLK5 O3 QSPI5 output – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Table 2-10 Port 20 Functions Pin Symbol Ctrl Type Function N25 P20.0 I MP / PU1 / VEXT General-purpose input TIN59 RXDCAN3C GTM input CAN node 3 input RXDCANr1C CAN node 1 input (MultiCANr+) T6EUDA GPT120 input REQ9 SCU input SYSCLK HSCT input TGI0 OCDS input P20.0 O0 General-purpose output TOUT59 O1 GTM output ATX3 O2 ASCLIN3 output ASCLK3 O3 ASCLIN3 output – O4 Reserved SYSCLK O5 HSCT output – O6 Reserved – O7 Reserved TGO0 HWOU T OCDS; ENx Data Sheet TOC-60 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-10 Port 20 Functions (cont’d) Pin Symbol Ctrl Type Function M24 P20.1 I LP / PU1 / VEXT General-purpose input TIN60 TGI1 N24 OCDS input P20.1 O0 General-purpose output TOUT60 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved TGO1 HWOU T OCDS; ENx P20.2 I LP / PU1 / VEXT TESTMODE M25 GTM input General-purpose input This pin is latched at power on reset release to enter test mode. OCDS input P20.2 O0 Output function not available – O1 Output function not available – O2 Output function not available – O3 Output function not available – O4 Output function not available – O5 Output function not available – O6 Output function not available – O7 Output function not available P20.3 I TIN61 T6INA ARX3C LP / PU1 / VEXT General-purpose input GTM input GPT120 input ASCLIN3 input P20.3 O0 General-purpose output TOUT61 O1 GTM output ATX3 O2 ASCLIN3 output SLSO09 O3 QSPI0 output SLSO29 O4 QSPI2 output TXDCAN3 O5 CAN node 3 output TXDCANr1 O6 CAN node 1 output (MultiCANr+) – O7 Reserved Data Sheet TOC-61 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-10 Port 20 Functions (cont’d) Pin Symbol Ctrl Type Function L22 P20.6 I LP / PU1 / VEXT General-purpose input TIN62 L24 P20.6 O0 TOUT62 O1 GTM output ARTS1 O2 ASCLIN1 output SLSO08 O3 QSPI0 output SLSO28 O4 QSPI2 output – O5 Reserved WDT2LCK O6 SCU output – O7 Reserved P20.7 I TIN63 ACTS1A LP / PU1 / VEXT RXDCAN0B L25 GTM input General-purpose output General-purpose input GTM input ASCLIN1 input CAN node 0 input P20.7 O0 General-purpose output TOUT63 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved WDT1LCK O6 SCU output COUT63 O7 CCU61 output P20.8 I TIN64 MP / PU1 / VEXT General-purpose input GTM input P20.8 O0 TOUT64 O1 GTM output ASLSO1 O2 ASCLIN1 output SLSO00 O3 QSPI0 output SLSO10 O4 QSPI1 output TXDCAN0 O5 CAN node 0 output WDT0LCK O6 SCU output CC60 O7 CCU61 output Data Sheet General-purpose output TOC-62 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-10 Port 20 Functions (cont’d) Pin Symbol Ctrl Type Function K22 P20.9 I LP / PU1 / VEXT General-purpose input TIN65 ARX1C K24 ASCLIN1 input RXDCAN3E CAN node 3 input REQ11 SCU input SLSI0B QSPI0 input P20.9 O0 General-purpose output TOUT65 O1 GTM output – O2 Reserved SLSO01 O3 QSPI0 output SLSO11 O4 QSPI1 output – O5 Reserved WDTSLCK O6 SCU output CC61 O7 CCU61 output P20.10 I TIN66 K25 GTM input MP / PU1 / VEXT General-purpose input GTM input P20.10 O0 TOUT66 O1 GTM output ATX1 O2 ASCLIN1 output SLSO06 O3 QSPI0 output SLSO27 O4 QSPI2 output TXDCAN3 O5 CAN node 3 output ASCLK1 O6 ASCLIN1 output CC62 O7 CCU61 output P20.11 I TIN67 SCLK0A MP / PU1 / VEXT General-purpose output General-purpose input GTM input QSPI0 input P20.11 O0 General-purpose output TOUT67 O1 GTM output – O2 Reserved SCLK0 O3 QSPI0 output – O4 Reserved – O5 Reserved – O6 Reserved COUT60 O7 CCU61 output Data Sheet TOC-63 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-10 Port 20 Functions (cont’d) Pin Symbol Ctrl Type Function J24 P20.12 I MP / PU1 / VEXT General-purpose input TIN68 MRST0A J25 QSPI0 input P20.12 O0 General-purpose output TOUT68 O1 GTM output – O2 Reserved MRST0 O3 QSPI0 output MTSR0 O4 QSPI0 output – O5 Reserved – O6 Reserved COUT61 O7 CCU61 output P20.13 I TIN69 SLSI0A H25 GTM input MP / PU1 / VEXT General-purpose input GTM input QSPI0 input P20.13 O0 General-purpose output TOUT69 O1 GTM output – O2 Reserved SLSO02 O3 QSPI0 output SLSO12 O4 QSPI1 output SCLK0 O5 QSPI0 output – O6 Reserved COUT62 O7 CCU61 output P20.14 I TIN70 MTSR0A MP / PU1 / VEXT General-purpose input GTM input QSPI0 input P20.14 O0 General-purpose output TOUT70 O1 GTM output – O2 Reserved MTSR0 O3 QSPI0 output – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-64 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-11 Port 21 Functions Pin Symbol Ctrl Type Function R22 P21.0 I LVDSH_N/ PU1 / VDDP3 General-purpose input TIN51 MRST4DN HOLD P22 GTM input QSPI4 input (LVDS) EBU input P21.0 O0 General-purpose output TOUT51 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved ETHMDC O6 ETH output BAABA0 O7 EBU output (combined for BAA and BA0) HSM1 O HSM output P21.1 I TIN52 ETHMDIOB LVDSH_P/ PU1 / VDDP3 General-purpose input GTM input ETH input (Not for production purposes) MRST4DP QSPI4 input (LVDS) WAIT EBU input P21.1 O0 General-purpose output TOUT52 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved ETHMDIO O6 ETH output (Not for production purposes) BREQBA1 O7 EBU output (combined for BREQ and BA1) HSM2 O HSM output Data Sheet TOC-65 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-11 Port 21 Functions (cont’d) Pin Symbol Ctrl Type Function R24 P21.2 I LVDSH_N/ PU1 / VDDP3 General-purpose input TIN53 MRST2CN P24 GTM input QSPI2 input (LVDS) MRST4CN QSPI4 input (LVDS) ARX3GN ASCLIN3 input (LVDS) EMGSTOPB SCU input RXDN HSCT input (LVDS) P21.2 O0 General-purpose output TOUT53 O1 GTM output ASLSO3 O2 ASCLIN3 output – O3 Reserved – O4 Reserved ETHMDC O5 ETH output SDRAMA8 O6 EBU output – O7 Reserved P21.3 I TIN54 MRST2CP LVDSH_P/ PU1 / VDDP3 General-purpose input GTM input QSPI2 input (LVDS) MRST4CP QSPI4 input (LVDS) ARX3GP ASCLIN3 input (LVDS) RXDP HSCT input (LVDS) P21.3 O0 General-purpose output TOUT54 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved SDRAMA9 O6 EBU output – O7 Reserved ETHMDIOD HWOUT ETH input/output Data Sheet TOC-66 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-11 Port 21 Functions (cont’d) Pin Symbol Ctrl Type Function R25 P21.4 I LVDSH_N/ PU1 / VDDP3 General-purpose input TIN55 P25 P21.4 O0 TOUT55 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved SDRAMA10 O6 EBU output – O7 Reserved TXDN HSCT HSCT output (LVDS) P21.5 I TIN56 N22 GTM input LVDSH_P/ PU1 / VDDP3 General-purpose output General-purpose input GTM input P21.5 O0 TOUT56 O1 GTM output ASCLK3 O2 ASCLIN3 output – O3 Reserved – O4 Reserved – O5 Reserved SDRAMA11 O6 EBU output – O7 Reserved TXDP HSCT HSCT output (LVDS) P21.6 I TIN57 ARX3F A2 / PU / VDDP3 General-purpose output General-purpose input GTM input ASCLIN3 input TGI2 OCDS input TDI OCDS (JTAG) input T5EUDA GPT120 input P21.6 O0 General-purpose output TOUT57 O1 GTM output ASLSO3 O2 ASCLIN3 output – O3 Reserved – O4 Reserved SYSCLK O5 HSCT output SDRAMA12 O6 EBU output T3OUT O7 GPT120 output TGO2 HWOUT OCDS; ENx Data Sheet TOC-67 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-11 Port 21 Functions (cont’d) Pin Symbol Ctrl Type Function N21 P21.7 I A2 / PU / VDDP3 General-purpose input TIN58 DAP2 GTM input OCDS (3-Pin DAP) input In the 3-Pin DAP mode this pin is used as DAP2. In the 2-PIN DAP mode this pin is used as P21.7 and controlled by the related port control logic TGI3 OCDS input ETHRXERB ETH input T5INA GPT120 input P21.7 O0 General-purpose output TOUT58 O1 GTM output ATX3 O2 ASCLIN3 output ASCLK3 O3 ASCLIN3 output – O4 Reserved – O5 Reserved SDRAMA13 O6 EBU output T6OUT O7 GPT120 output TGO3 HWOUT OCDS; ENx TDO OCDS (JTAG); ENx The JTAG TDO function is overlayed with P21.7 via a double bond. In JTAG mode this pin is used as TDO, after power-on reset it is HighZ. DAP2 OCDS (3-Pin DAP); ENx In the 3-Pin DAP mode this pin is used as DAP2. Table 2-12 Port 22 Functions Pin Symbol Ctrl Type Function W25 P22.0 I LVDSM_N / PU1 / VEXT General-purpose input TIN47 MTSR4B GTM input QSPI4 input P22.0 O0 General-purpose output TOUT47 O1 GTM output ATX3N O2 ASCLIN3 output (LVDS) MTSR4 O3 QSPI4 output SCLK4N O4 QSPI4 output (LVDS) FCLN1 O5 MSC1 output (LVDS) FCLND1 O6 MSC1 output (LVDS) – O7 Reserved Data Sheet TOC-68 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-12 Port 22 Functions (cont’d) Pin Symbol Ctrl Type Function W24 P22.1 I LVDSM_P / PU1 / VEXT General-purpose input TIN48 MRST4B Y25 QSPI4 input P22.1 O0 General-purpose output TOUT48 O1 GTM output ATX3P O2 ASCLIN3 output (LVDS) MRST4 O3 QSPI4 output SCLK4P O4 QSPI4 output (LVDS) FCLP1 O5 MSC1 output (LVDS) – O6 Reserved – O7 Reserved P22.2 I TIN49 SLSI4B Y24 GTM input LVDSM_N / PU1 / VEXT General-purpose input GTM input QSPI4 input P22.2 O0 General-purpose output TOUT49 O1 GTM output – O2 Reserved SLSO43 O3 QSPI4 output MTSR4N O4 QSPI4 output (LVDS) SON1 O5 MSC1 output (LVDS) SOND1 O6 MSC1 output (LVDS) – O7 Reserved P22.3 I TIN50 SCLK4B LVDSM_P / PU1 / VEXT General-purpose input GTM input QSPI4 input P22.3 O0 General-purpose output TOUT50 O1 GTM output – O2 Reserved SCLK4 O3 QSPI4 output MTSR4P O4 QSPI4 output (LVDS) SOP1 O5 MSC1 output (LVDS) – O6 Reserved – O7 Reserved Data Sheet TOC-69 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-12 Port 22 Functions (cont’d) Pin Symbol Ctrl Type Function W21 P22.4 I LP / PU1 / VEXT General-purpose input TIN130 W22 GTM input P22.4 O0 TOUT130 O1 GTM output – O2 Reserved – O3 Reserved SLSO012 O4 QSPI0 output PSITX4 O5 PSI5 output – O6 Reserved – O7 Reserved P22.5 I TIN131 MTSR0C General-purpose output General-purpose input LP / PU1 / VEXT GTM input QSPI0 input PSIRX4B V21 PSI5 input P22.5 O0 General-purpose output TOUT131 O1 GTM output – O2 Reserved – O3 Reserved MTSR0 O4 QSPI0 output – O5 Reserved – O6 Reserved – O7 Reserved P22.6 I TIN132 MRST0C General-purpose input LP / PU1 / VEXT GTM input QSPI0 input P22.6 O0 General-purpose output TOUT132 O1 GTM output – O2 Reserved – O3 Reserved MRST0 O4 QSPI0 output – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-70 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-12 Port 22 Functions (cont’d) Pin Symbol Ctrl Type Function V22 P22.7 I LP / PU1 / VEXT General-purpose input TIN133 SCLK0C U21 QSPI0 input P22.7 O0 General-purpose output TOUT133 O1 GTM output – O2 Reserved – O3 Reserved SCLK0 O4 QSPI0 output – O5 Reserved – O6 Reserved – O7 Reserved P22.8 I TIN134 SCLK0B U22 GTM input General-purpose input LP / PU1 / VEXT GTM input QSPI0 input P22.8 O0 General-purpose output TOUT134 O1 GTM output – O2 Reserved – O3 Reserved SCLK0 O4 QSPI0 output – O5 Reserved – O6 Reserved – O7 Reserved P22.9 I TIN135 MRST0B General-purpose input LP / PU1 / VEXT GTM input QSPI0 input P22.9 O0 General-purpose output TOUT135 O1 GTM output – O2 Reserved – O3 Reserved MRST0 O4 QSPI0 output – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-71 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-12 Port 22 Functions (cont’d) Pin Symbol Ctrl Type Function T21 P22.10 I LP / PU1 / VEXT General-purpose input TIN136 MTSR0B T22 GTM input QSPI0 input P22.10 O0 General-purpose output TOUT136 O1 GTM output – O2 Reserved – O3 Reserved MTSR0 O4 QSPI0 output – O5 Reserved – O6 Reserved – O7 Reserved P22.11 I TIN137 General-purpose input LP / PU1 / VEXT GTM input P22.11 O0 General-purpose output TOUT137 O1 GTM output – O2 Reserved – O3 Reserved SLSO010 O4 QSPI0 output – O5 Reserved – O6 Reserved – O7 Reserved Table 2-13 Port 23 Functions Pin Symbol Ctrl Type Function AC25 P23.0 I LP / PU1 / VEXT General-purpose input TIN41 GTM input P23.0 O0 TOUT41 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet General-purpose output TOC-72 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-13 Port 23 Functions (cont’d) Pin Symbol Ctrl Type Function AB24 P23.1 I MP+ / PU1 / VEXT General-purpose input TIN42 SDI10 AB25 MSC1 input P23.1 O0 General-purpose output TOUT42 O1 GTM output ARTS1 O2 ASCLIN1 output SLSO46 O3 QSPI4 output GTMCLK0 O4 GTM output – O5 Reserved EXTCLK0 O6 SCU output – O7 Reserved P23.2 I TIN43 AA24 GTM input LP / PU1 / VEXT General-purpose input GTM input P23.2 O0 TOUT43 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P23.3 I TIN44 INJ10 LP / PU1 / VEXT General-purpose output General-purpose input GTM input MSC1 input P23.3 O0 General-purpose output TOUT44 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-73 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-13 Port 23 Functions (cont’d) Pin Symbol Ctrl Type Function AA25 P23.4 I MP+ / PU1 / VEXT General-purpose input TIN45 AA22 P23.4 O0 TOUT45 O1 GTM output – O2 Reserved SLSO45 O3 QSPI4 output END12 O4 MSC1 output EN10 O5 MSC1 output – O6 Reserved – O7 Reserved P23.5 I TIN46 Y22 GTM input MP+ / PU1 / VEXT General-purpose output General-purpose input GTM input P23.5 O0 TOUT46 O1 GTM output – O2 Reserved SLSO44 O3 QSPI4 output END13 O4 MSC1 output EN11 O5 MSC1 output – O6 Reserved – O7 Reserved P23.6 I TIN138 LP / PU1 / VEXT General-purpose output General-purpose input GTM input P23.6 O0 TOUT138 O1 GTM output – O2 Reserved – O3 Reserved SLSO011 O4 QSPI0 output – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet General-purpose output TOC-74 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-13 Port 23 Functions (cont’d) Pin Symbol Ctrl Type Function Y21 P23.7 I LP / PU1 / VEXT General-purpose input TIN139 GTM input P23.7 O0 General-purpose output TOUT139 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Table 2-14 Port 24 Functions Pin Symbol Ctrl Type Function U29 P24.0 I A2 / PU1 / VEBU General-purpose input TIN222 P24.0 O0 TOUT222 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ11 HWOU T EBU Data Bus Line (SDRAM) A11 U30 GTM input P24.1 I TIN223 General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P24.1 O0 TOUT223 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ15 HWOU T EBU Data Bus Line (SDRAM) A15 Data Sheet General-purpose output EBU output TOC-75 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-14 Port 24 Functions (cont’d) Pin Symbol Ctrl Type Function T29 P24.2 I A2 / PU1 / VEBU General-purpose input TIN224 P24.2 O0 TOUT224 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ14 HWOU T EBU Data Bus Line (SDRAM) A14 T30 P24.3 I TIN225 General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P24.3 O0 TOUT225 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ13 HWOU T EBU Data Bus Line (SDRAM) A13 R29 GTM input P24.4 I TIN226 General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P24.4 O0 TOUT226 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ9 HWOU T EBU Data Bus Line (SDRAM) A9 Data Sheet General-purpose output EBU output TOC-76 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-14 Port 24 Functions (cont’d) Pin Symbol Ctrl Type Function R30 P24.5 I A2 / PU1 / VEBU General-purpose input TIN227 P24.5 O0 TOUT227 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ12 HWOU T EBU Data Bus Line (SDRAM) A12 P29 P24.6 I TIN228 General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P24.6 O0 TOUT228 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ5 HWOU T EBU Data Bus Line (SDRAM) A5 P30 GTM input P24.7 I TIN229 General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P24.7 O0 TOUT229 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ8 HWOU T EBU Data Bus Line (SDRAM) A8 Data Sheet General-purpose output EBU output TOC-77 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-14 Port 24 Functions (cont’d) Pin Symbol Ctrl Type Function N29 P24.8 I A2 / PU1 / VEBU General-purpose input TIN230 P24.8 O0 TOUT230 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ10 HWOU T EBU Data Bus Line (SDRAM) A10 N30 P24.9 I TIN231 General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P24.9 O0 TOUT231 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ6 HWOU T EBU Data Bus Line (SDRAM) A6 M29 GTM input P24.10 I TIN232 General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P24.10 O0 TOUT232 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ4 HWOU T EBU Data Bus Line (SDRAM) A4 Data Sheet General-purpose output EBU output TOC-78 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-14 Port 24 Functions (cont’d) Pin Symbol Ctrl Type Function M30 P24.11 I A2 / PU1 / VEBU General-purpose input TIN233 P24.11 O0 TOUT233 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ3 HWOU T EBU Data Bus Line (SDRAM) A3 L29 P24.12 I TIN234 General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P24.12 O0 TOUT234 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ1 HWOU T EBU Data Bus Line (SDRAM) A1 L30 GTM input P24.13 I TIN235 General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P24.13 O0 TOUT235 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ2 HWOU T EBU Data Bus Line (SDRAM) A2 Data Sheet General-purpose output EBU output TOC-79 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-14 Port 24 Functions (cont’d) Pin Symbol Ctrl Type Function K29 P24.14 I A2 / PU1 / VEBU General-purpose input TIN236 P24.14 O0 TOUT236 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ0 HWOU T EBU Data Bus Line (SDRAM) A0 K30 GTM input P24.15 I TIN237 General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P24.15 O0 TOUT237 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ7 HWOU T EBU Data Bus Line (SDRAM) A7 Data Sheet General-purpose output EBU output TOC-80 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-15 Port 25 Functions Pin Symbol Ctrl Type Function AG30 P25.0 I A2 / PU1 / VEBU General-purpose input TIN206 SDCLKI O0 General-purpose output TOUT206 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved BFCLKO HWOU T EBU output P25.1 I TIN207 EBU output A2 / PU1 / VEBU General-purpose input GTM input P25.1 O0 TOUT207 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved RD HWOU T EBU output RAS AF29 EBU input P25.0 SDCLKO AF30 GTM input P25.2 I TIN208 General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P25.2 O0 TOUT208 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved RD/WR HWOU T EBU output WR Data Sheet General-purpose output EBU output TOC-81 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-15 Port 25 Functions (cont’d) Pin Symbol Ctrl Type Function AE30 P25.3 I A2 / PU1 / VEBU General-purpose input TIN209 HOLDA O0 General-purpose output TOUT209 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved BAABA0 O7 EBU output (combined for BAA and BA0) CS2 HWOU T EBU output EBU output HOLDA P25.4 EBU output I TIN210 A2 / PU1 / VEBU General-purpose input GTM input P25.4 O0 TOUT210 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved CS1 HWOU T EBU output DQM0 AD30 EBU input P25.3 DQM1 AE29 GTM input P25.5 I TIN211 General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P25.5 O0 TOUT211 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved CS0 HWOU T EBU output Data Sheet General-purpose output TOC-82 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-15 Port 25 Functions (cont’d) Pin Symbol Ctrl Type Function W29 P25.6 I A2 / PU1 / VEBU General-purpose input AD29 P25.6 O0 TOUT212 O1 – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved CKE HWOU T EBU output P25.7 I TIN213 GTM output General-purpose input GTM input P25.7 O0 TOUT213 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved ADV HWOU T EBU output CAS AC29 A2 / PU1 / VEBU General-purpose output P25.8 I TIN214 General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P25.8 O0 TOUT214 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved A23 O5 EBU output SDRAMA0 O6 EBU output – O7 Reserved BC0 HWOU T EBU output Data Sheet General-purpose output TOC-83 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-15 Port 25 Functions (cont’d) Pin Symbol Ctrl Type Function AC30 P25.9 I A2 / PU1 / VEBU General-purpose input TIN215 AB29 P25.9 O0 TOUT215 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved A22 O5 EBU output SDRAMA1 O6 EBU output – O7 Reserved BC1 HWOU T EBU output P25.10 I TIN216 AB30 GTM input A2 / PU1 / VEBU General-purpose output General-purpose input GTM input P25.10 O0 TOUT216 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved A21 O5 EBU output SDRAMA2 O6 EBU output – O7 Reserved BC2 HWOU T EBU output P25.11 I TIN217 A2 / PU1 / VEBU General-purpose output General-purpose input GTM input P25.11 O0 TOUT217 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved A20 O5 EBU output SDRAMA3 O6 EBU output – O7 Reserved BC3 HWOU T EBU output Data Sheet General-purpose output TOC-84 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-15 Port 25 Functions (cont’d) Pin Symbol Ctrl Type Function AA29 P25.12 I A2 / PU1 / VEBU General-purpose input TIN218 AA30 P25.12 O0 TOUT218 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved SDRAMA4 O6 EBU output – O7 Reserved A19 HWOU T EBU output P25.13 I TIN219 Y29 GTM input A2 / PU1 / VEBU General-purpose output General-purpose input GTM input P25.13 O0 TOUT219 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved SDRAMA5 O6 EBU output – O7 Reserved A17 HWOU T EBU output P25.14 I TIN220 A2 / PU1 / VEBU General-purpose output General-purpose input GTM input P25.14 O0 TOUT220 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved SDRAMA6 O6 EBU output – O7 Reserved A18 HWOU T EBU output Data Sheet General-purpose output TOC-85 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-15 Port 25 Functions (cont’d) Pin Symbol Ctrl Type Function Y30 P25.15 I A2 / PU1 / VEBU General-purpose input TIN221 GTM input P25.15 O0 General-purpose output TOUT221 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved SDRAMA7 O6 EBU output – O7 Reserved A16 HWOU T EBU output Table 2-16 Port 26 Functions Pin Symbol Ctrl Type Function AG29 P26.0 I LP / PU1 / VFLEXE General-purpose input TIN212 BFCLKI GTM input EBU input P26.0 O0 General-purpose output TOUT212 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-86 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-17 Port 30 Functions Pin Symbol Ctrl Type Function AJ21 P30.0 I MP / PU1 / VFLEXE General-purpose input TIN190 AK21 P30.0 O0 TOUT190 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD14 HWOU T EBU Address / Data Bus Line P30.1 I TIN191 AJ22 GTM input MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P30.1 O0 TOUT191 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD11 HWOU T EBU Address / Data Bus Line P30.2 I TIN192 MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P30.2 O0 TOUT192 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD12 HWOU T EBU Address / Data Bus Line Data Sheet General-purpose output TOC-87 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-17 Port 30 Functions (cont’d) Pin Symbol Ctrl Type Function AK22 P30.3 I MP / PU1 / VFLEXE General-purpose input TIN193 AJ23 P30.3 O0 TOUT193 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD15 HWOU T EBU Address / Data Bus Line P30.4 I TIN194 AK23 GTM input MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P30.4 O0 TOUT194 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD8 HWOU T EBU Address / Data Bus Line P30.5 I TIN195 MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P30.5 O0 TOUT195 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD13 HWOU T EBU Address / Data Bus Line Data Sheet General-purpose output TOC-88 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-17 Port 30 Functions (cont’d) Pin Symbol Ctrl Type Function AJ24 P30.6 I MP / PU1 / VFLEXE General-purpose input TIN196 AK24 P30.6 O0 TOUT196 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD4 HWOU T EBU Address / Data Bus Line P30.7 I TIN197 AJ25 GTM input MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P30.7 O0 TOUT197 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD7 HWOU T EBU Address / Data Bus Line P30.8 I TIN198 MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P30.8 O0 TOUT198 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD3 HWOU T EBU Address / Data Bus Line Data Sheet General-purpose output TOC-89 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-17 Port 30 Functions (cont’d) Pin Symbol Ctrl Type Function AK25 P30.9 I MP / PU1 / VFLEXE General-purpose input TIN199 AJ26 P30.9 O0 TOUT199 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD0 HWOU T EBU Address / Data Bus Line P30.10 I TIN200 AK26 GTM input MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P30.10 O0 TOUT200 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD5 HWOU T EBU Address / Data Bus Line P30.11 I TIN201 MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P30.11 O0 TOUT201 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD10 HWOU T EBU Address / Data Bus Line Data Sheet General-purpose output TOC-90 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-17 Port 30 Functions (cont’d) Pin Symbol Ctrl Type Function AJ27 P30.12 I MP / PU1 / VFLEXE General-purpose input TIN202 AK27 P30.12 O0 TOUT202 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD9 HWOU T EBU Address / Data Bus Line P30.13 I TIN203 AJ28 GTM input MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P30.13 O0 TOUT203 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD2 HWOU T EBU Address / Data Bus Line P30.14 I TIN204 MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P30.14 O0 TOUT204 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD1 HWOU T EBU Address / Data Bus Line Data Sheet General-purpose output TOC-91 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-17 Port 30 Functions (cont’d) Pin Symbol Ctrl Type Function AK28 P30.15 I MP / PU1 / VFLEXE General-purpose input TIN205 GTM input P30.15 O0 General-purpose output TOUT205 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD6 HWOU T EBU Address / Data Bus Line Table 2-18 Port 31 Functions Pin Symbol Ctrl Type Function AJ12 P31.0 I MP / PU1 / VFLEXE General-purpose input TIN174 AK12 GTM input P31.0 O0 TOUT174 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD30 HWOU T EBU Address / Data Bus Line P31.1 I TIN175 MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P31.1 O0 TOUT175 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD29 HWOU T EBU Address / Data Bus Line Data Sheet General-purpose output TOC-92 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-18 Port 31 Functions (cont’d) Pin Symbol Ctrl Type Function AJ13 P31.2 I MP / PU1 / VFLEXE General-purpose input TIN176 AK13 P31.2 O0 TOUT176 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD28 HWOU T EBU Address / Data Bus Line P31.3 I TIN177 AJ14 GTM input MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P31.3 O0 TOUT177 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD26 HWOU T EBU Address / Data Bus Line P31.4 I TIN178 MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P31.4 O0 TOUT178 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD24 HWOU T EBU Address / Data Bus Line Data Sheet General-purpose output TOC-93 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-18 Port 31 Functions (cont’d) Pin Symbol Ctrl Type Function AK14 P31.5 I MP / PU1 / VFLEXE General-purpose input TIN179 AJ15 P31.5 O0 TOUT179 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD23 HWOU T EBU Address / Data Bus Line P31.6 I TIN180 AK15 GTM input MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P31.6 O0 TOUT180 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD20 HWOU T EBU Address / Data Bus Line P31.7 I TIN181 MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P31.7 O0 TOUT181 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD16 HWOU T EBU Address / Data Bus Line Data Sheet General-purpose output TOC-94 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-18 Port 31 Functions (cont’d) Pin Symbol Ctrl Type Function AJ16 P31.8 I MP / PU1 / VFLEXE General-purpose input TIN182 AK16 P31.8 O0 TOUT182 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD31 HWOU T EBU Address / Data Bus Line P31.9 I TIN183 AJ17 GTM input MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P31.9 O0 TOUT183 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD27 HWOU T EBU Address / Data Bus Line P31.10 I TIN184 MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P31.10 O0 TOUT184 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD21 HWOU T EBU Address / Data Bus Line Data Sheet General-purpose output TOC-95 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-18 Port 31 Functions (cont’d) Pin Symbol Ctrl Type Function AK17 P31.11 I MP / PU1 / VFLEXE General-purpose input TIN185 AJ18 P31.11 O0 TOUT185 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD25 HWOU T EBU Address / Data Bus Line P31.12 I TIN186 AK18 GTM input MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P31.12 O0 TOUT186 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD19 HWOU T EBU Address / Data Bus Line P31.13 I TIN187 MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P31.13 O0 TOUT187 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD22 HWOU T EBU Address / Data Bus Line Data Sheet General-purpose output TOC-96 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-18 Port 31 Functions (cont’d) Pin Symbol Ctrl Type Function AJ19 P31.14 I MP / PU1 / VFLEXE General-purpose input TIN188 AK19 GTM input P31.14 O0 TOUT188 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD18 HWOU T EBU Address / Data Bus Line P31.15 I TIN189 MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P31.15 O0 TOUT189 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD17 HWOU T EBU Address / Data Bus Line Data Sheet General-purpose output TOC-97 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-19 Port 32 Functions Pin Symbol Ctrl Type Function AE22 P32.0 I LP / PX/ VEXT General-purpose input TIN36 FDEST VGATE1N GTM input PMU input SMPS mode: analog output. External Pass Device gate control for EVR13 P32.0 O0 General-purpose output TOUT36 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P32.2 AE23 I TIN38 ARX3D LP / PU1 / VEXT General-purpose input GTM input ASCLIN3 input RXDCAN3B CAN node 3 input RXDCANr1D CAN node 1 input (MultiCANr+) P32.2 O0 General-purpose output TOUT38 O1 GTM output ATX3 O2 ASCLIN3 output – O3 Reserved – O4 Reserved – O5 Reserved DCDCSYNC O6 SCU output – O7 Reserved P32.3 AE24 I TIN39 LP / PU1 / VEXT General-purpose input GTM input P32.3 O0 TOUT39 O1 GTM output ATX3 O2 ASCLIN3 output – O3 Reserved ASCLK3 O4 ASCLIN3 output TXDCAN3 O5 CAN node 3 output TXDCANr1 O6 CAN node 1 output (MultiCANr+) – O7 Reserved Data Sheet General-purpose output TOC-98 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-19 Port 32 Functions (cont’d) Pin Symbol Ctrl Type Function AD23 P32.4 I MP+ / PU1 / VEXT General-purpose input TIN40 ACTS1B SDI12 GTM input ASCLIN1 input MSC1 input P32.4 O0 General-purpose output TOUT40 O1 GTM output – O2 Reserved END12 O3 MSC1 output GTMCLK1 O4 GTM output EN10 O5 MSC1 output EXTCLK1 O6 SCU output COUT63 O7 CCU60 output P32.5 AA20 I TIN140 LP / PU1 / VEXT General-purpose input GTM input P32.5 O0 TOUT140 O1 GTM output ATX2 O2 ASCLIN2 output – O3 Reserved – O4 Reserved – O5 Reserved TXDCAN2 O6 CAN node 2 output – O7 Reserved P32.6 AB20 I TGI4 TIN141 LP / PU1 / VEXT General-purpose output General-purpose input OCDS input GTM input RXDCAN2C CAN node 2 input ARX2F ASCLIN2 input P32.6 O0 General-purpose output TOUT141 O1 GTM output – O2 Reserved – O3 Reserved SLSO212 O4 QSPI2 output – O5 Reserved – O6 Reserved – O7 Reserved TGO4 HWOU T OCDS; ENx Data Sheet TOC-99 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-19 Port 32 Functions (cont’d) Pin Symbol Ctrl Type Function AB21 P32.7 I LP / PU1 / VEXT General-purpose input TIN142 TGI5 GTM input OCDS input P32.7 O0 General-purpose output TOUT142 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved TGO5 HWOU T OCDS; ENx Table 2-20 Port 33 Functions Pin Symbol Ctrl Type Function AD15 P33.0 I LP / PU1 / VEXT General-purpose input TIN22 DSITR0E GTM input DSADC channel 0 input E P33.0 O0 General-purpose output TOUT22 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved VADCG2BFL0 O6 VADC output – O7 Reserved Data Sheet TOC-100 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-20 Port 33 Functions (cont’d) Pin Symbol Ctrl Type Function AE15 P33.1 I LP / PU1 / VEXT General-purpose input TIN23 PSIRX0C GTM input PSI5 input SENT9C SENT input DSCIN2B DSADC channel 2 input B DSITR1E DSADC channel 1 input E P33.1 O0 General-purpose output TOUT23 O1 GTM output ASLSO3 O2 ASCLIN3 output SCLK2 O3 QSPI2 output DSCOUT2 O4 DSADC channel 2 output VADCEMUX02 O5 VADC output VADCG2BFL1 O6 VADC output – O7 Reserved P33.2 AD16 I TIN24 SENT8C LP / PU1 / VEXT General-purpose input GTM input SENT input DSDIN2B DSADC channel 2 input B DSITR2E DSADC channel 2 input E P33.2 O0 General-purpose output TOUT24 O1 GTM output ASCLK3 O2 ASCLIN3 output SLSO210 O3 QSPI2 output PSITX0 O4 PSI5 output VADCEMUX01 O5 VADC output VADCG2BFL2 O6 VADC output – O7 Reserved Data Sheet TOC-101 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-20 Port 33 Functions (cont’d) Pin Symbol Ctrl Type Function AE16 P33.3 I LP / PU1 / VEXT General-purpose input TIN25 PSIRX1C GTM input PSI5 input SENT7C SENT input DSCIN1B DSADC channel 1 input B P33.3 O0 General-purpose output TOUT25 O1 GTM output – O2 Reserved – O3 Reserved DSCOUT1 O4 DSADC channel 1 output VADCEMUX00 O5 VADC output VADCG2BFL3 O6 VADC output – O7 Reserved P33.4 AD17 I TIN26 SENT6C LP / PU1 / VEXT General-purpose input GTM input SENT input CTRAPC CCU61 input DSDIN1B DSADC channel 1 input DSITR0F DSADC channel 0 input F P33.4 O0 General-purpose output TOUT26 O1 GTM output ARTS2 O2 ASCLIN2 output SLSO212 O3 QSPI2 output PSITX1 O4 PSI5 output VADCEMUX12 O5 VADC output VADCG0BFL0 O6 VADC output – O7 Reserved Data Sheet TOC-102 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-20 Port 33 Functions (cont’d) Pin Symbol Ctrl Type Function AE17 P33.5 I LP / PU1 / VEXT General-purpose input TIN27 ACTS2B GTM input ASCLIN2 input PSIRX2C PSI5 input PSISRXC PSI5-S input SENT5C SENT input CCPOS2C CCU61 input T4EUDB GPT120 input DSCIN0B DSADC channel 0 input B DSITR1F DSADC channel 1 input F P33.5 O0 General-purpose output TOUT27 O1 GTM output SLSO07 O2 QSPI0 output SLSO17 O3 QSPI1 output DSCOUT0 O4 DSADC channel 0 output VADCEMUX11 O5 VADC output VADCG0BFL1 O6 VADC output – O7 Reserved P33.6 AD18 I TIN28 SENT4C LP / PU1 / VEXT General-purpose input GTM input SENT input CCPOS1C CCU61 input T2EUDB GPT120 input DSDIN0B DSADC channel 0 input B DSITR2F DSADC channel 2 input F P33.6 O0 General-purpose output TOUT28 O1 GTM output ASLSO2 O2 ASCLIN2 output SLSO211 O3 QSPI2 output PSITX2 O4 PSI5 output VADCEMUX10 O5 VADC output VADCG1BFL0 O6 VADC output PSISTX O7 PSI5-S output Data Sheet TOC-103 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-20 Port 33 Functions (cont’d) Pin Symbol Ctrl Type Function AE18 P33.7 I LP / PU1 / VEXT General-purpose input TIN29 RXDCAN0E GTM input CAN node 0 input REQ8 SCU input CCPOS0C CCU61 input T2INB GPT120 input P33.7 O0 General-purpose output TOUT29 O1 GTM output ASCLK2 O2 ASCLIN2 output SLSO47 O3 QSPI4 output – O4 Reserved – O5 Reserved VADCG1BFL1 O6 VADC output – O7 Reserved P33.8 AD19 I TIN30 ARX2E MP / HighZ / VEXT EMGSTOPA General-purpose input GTM input ASCLIN2 input SCU input P33.8 O0 General-purpose output TOUT30 O1 GTM output ATX2 O2 ASCLIN2 output SLSO42 O3 QSPI4 output – O4 Reserved TXDCAN0 O5 CAN node 0 output – O6 Reserved COUT62 O7 CCU61 output SMUFSP HWOU T SMU P33.9 AE19 I TIN31 HSIC3INA LP / PU1 / VEXT General-purpose input GTM input QSPI3 input P33.9 O0 General-purpose output TOUT31 O1 GTM output ATX2 O2 ASCLIN2 output SLSO41 O3 QSPI4 output ASCLK2 O4 ASCLIN2 output – O5 Reserved – O6 Reserved CC62 O7 CCU61 output Data Sheet TOC-104 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-20 Port 33 Functions (cont’d) Pin Symbol Ctrl Type Function AD20 P33.10 I MP / PU1 / VEXT General-purpose input TIN32 SLSI4A HSIC3INB GTM input QSPI4 input QSPI3 input P33.10 O0 General-purpose output TOUT32 O1 GTM output SLSO16 O2 QSPI1 output SLSO40 O3 QSPI4 output ASLSO1 O4 ASCLIN1 output PSISCLK O5 PSI5-S output – O6 Reserved COUT61 O7 CCU61 output P33.11 AE20 I TIN33 SCLK4A MP / PU1 / VEXT General-purpose input GTM input QSPI4 input P33.11 O0 General-purpose output TOUT33 O1 GTM output ASCLK1 O2 ASCLIN1 output SCLK4 O3 QSPI4 output – O4 Reserved – O5 Reserved DSCGPWMN O6 DSADC channel output CC61 O7 CCU61 output P33.12 AD21 I TIN34 MTSR4A MP / PU1 / VEXT General-purpose input GTM input QSPI4 input P33.12 O0 General-purpose output TOUT34 O1 GTM output ATX1 O2 ASCLIN1 output MTSR4 O3 QSPI4 output ASCLK1 O4 ASCLIN1 output – O5 Reserved DSCGPWMP O6 DSADC output COUT60 O7 CCU61 output Data Sheet TOC-105 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-20 Port 33 Functions (cont’d) Pin Symbol Ctrl Type Function AE21 P33.13 I MP / PU1 / VEXT General-purpose input TIN35 ARX1F GTM input ASCLIN1 input MRST4A QSPI4 input DSSGNB DSADC channel input B INJ11 MSC1 input P33.13 O0 General-purpose output TOUT35 O1 GTM output ATX1 O2 ASCLIN1 output MRST4 O3 QSPI4 output SLSO26 O4 QSPI2 output – O5 Reserved DCDCSYNC O6 SCU output CC60 O7 CCU61 output P33.14 AA19 I TIN143 TGI6 SCLK2D LP / PU1 / VEXT General-purpose input GTM input OCDS input QSPI2 input P33.14 O0 General-purpose output TOUT143 O1 GTM output – O2 Reserved SCLK2 O3 QSPI2 output – O4 Reserved – O5 Reserved – O6 Reserved CC62 O7 CCU60 output TGO6 HWOU T OCDS; ENx Data Sheet TOC-106 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-20 Port 33 Functions (cont’d) Pin Symbol Ctrl Type Function AB19 P33.15 I LP / PU1 / VEXT General-purpose input TIN144 TGI7 GTM input OCDS input P33.15 O0 General-purpose output TOUT144 O1 GTM output – O2 Reserved SLSO211 O3 QSPI2 output – O4 Reserved – O5 Reserved – O6 Reserved COUT62 O7 CCU60 output TGO7 HWOU T OCDS; ENx Table 2-21 Port 34 Functions Pin Symbol Ctrl Type Function AB16 P34.1 I LP / PU1 / VEXT General-purpose input TIN146 AA17 GTM input P34.1 O0 TOUT146 O1 GTM output ATX0 O2 ASCLIN0 output – O3 Reserved TXDCAN0 O4 CAN node 0 output TXDCANr0 O5 CAN node 0 output (MultiCANr+) – O6 Reserved COUT63 O7 CCU60 output P34.2 I TIN147 ARX0D LP / PU1 / VEXT General-purpose output General-purpose input GTM input ASCLIN0 input RXDCAN0G CAN node 0 input RXDCANr0C CAN node 0 input (MultiCANr+) P34.2 O0 General-purpose output TOUT147 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved CC60 O7 CCU60 output Data Sheet TOC-107 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-21 Port 34 Functions (cont’d) Pin Symbol Ctrl Type Function AB17 P34.3 I LP / PU1 / VEXT General-purpose input TIN148 AA18 P34.3 O0 TOUT148 O1 GTM output – O2 Reserved – O3 Reserved SLSO210 O4 QSPI2 output – O5 Reserved – O6 Reserved COUT60 O7 CCU60 output P34.4 I TIN149 MRST2D AB18 GTM input LP / PU1 / VEXT General-purpose output General-purpose input GTM input QSPI2 input P34.4 O0 General-purpose output TOUT149 O1 GTM output – O2 Reserved – O3 Reserved MRST2 O4 QSPI2 output – O5 Reserved – O6 Reserved CC61 O7 CCU60 output P34.5 I TIN150 MTSR2D LP / PU1 / VEXT General-purpose input GTM input QSPI2 input P34.5 O0 General-purpose output TOUT150 O1 GTM output – O2 Reserved – O3 Reserved MTSR2 O4 QSPI2 output – O5 Reserved – O6 Reserved COUT61 O7 CCU60 output Data Sheet TOC-108 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-22 Port 40 Functions Pin Symbol Ctrl Type Function AD7 P40.0 I S/ HighZ / VDDM General-purpose input VADCG3.0 DS2PB VADC analog input channel 0 of group 3 DSADC: positive analog input of channel 2, pin B CCPOS0D CCU60 input SENT0A SENT input P40.1 AD6 I VADCG3.1 S/ HighZ / VDDM General-purpose inpu.t VADC analog input channel 1 of group 3 (with pull down diagnostics) DS2NB DSADC: negative analog input channel 2, pin B CCPOS1B CCU60 input SENT1A SENT input P40.2 AC7 I VADCG3.2 S/ HighZ / VDDM General-purpose inpu.t VADC analog input channel 2 of group 3 (with pull down diagnostics) CCPOS1D CCU60 input SENT2A SENT input P40.3 AC6 I VADCG3.3 S/ HighZ / VDDM General-purpose input VADC analog input channel 3 of group 3 (with pull down diagnostics) CCPOS2B CCU60 input SENT3A SENT input P40.4 W9 I VADCG4.0 CCPOS2D S/ HighZ / VDDM SENT4A P40.5 Y6 I CCPOS0D S/ HighZ / VDDM SENT5A P40.6 VADCG4.4 DS3PA VADC analog input channel 0 of group 4 CCU60 input SENT input VADCG4.1 V9 General-purpose input General-purpose input VADC analog input channel 1 of group 4 CCU61 input SENT input I S/ HighZ / VDDM General-purpose input VADC analog input channel 4 of group 4 DSADC: positive analog input of channel 3, pin A CCPOS1B CCU61 input SENT6A SENT input Data Sheet TOC-109 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-22 Port 40 Functions (cont’d) Pin Symbol Ctrl Type Function W7 P40.7 I S/ HighZ / VDDM General-purpose input VADCG4.5 DS3NA VADC analog input channel 5 of group 4 DSADC: negative analog input channel 3, pin A CCPOS1D CCU61 input SENT7A SENT input P40.8 V10 I VADCG4.6 DS3PB S/ HighZ / VDDM General-purpose input VADC analog input channel 6 of group 4 DSADC: positive analog input of channel 3, pin B CCPOS2B CCU61 input SENT8A SENT input P40.9 W6 I VADCG4.7 DS3NB S/ HighZ / VDDM General-purpose input VADC analog input channel 7 of group 4 DSADC: negative analog input channel 3, pin B CCPOS2D CCU61 input SENT9A SENT input P40.10 AA1 I VADCG10.3 DS8NB S/ HighZ / VDDM SENT10A P40.11 Y1 I DS8PA S/ HighZ / VDDM SENT11A P40.12 I DS8NA S/ HighZ / VDDM SENT12A P40.13 I DS9PA S/ HighZ / VDDM SENT13A P40.14 VADCG10.7 DS9NA SENT14A Data Sheet General-purpose input VADC analog input channel 4 of group 10 DSADC: positive analog input of channel 8, pin A General-purpose input VADC analog input channel 5 of group 10 DSADC: positive analog input of channel 8, pin A SENT input VADCG10.6 W2 DSADC: negative analog input channel 8, pin B SENT input VADCG10.5 W1 VADC analog input channel 3 of group 10 SENT input VADCG10.4 Y2 General-purpose input General-purpose input VADC analog input channel 6 of group 10 DSADC: positive analog input of channel 9, pin A SENT input I S/ HighZ / VDDM General-purpose input VADC analog input channel 7 of group 10 DSADC: positive analog input of channel 9, pin A SENT input TOC-110 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-23 Analog Inputs Pin Symbol Ctrl Type AA15 AN0 I D / HighZ / Analog input 0 VDDM VADC analog input channel 0 of group 0 VADCG0.0 DS1PA AN1 AB15 DSADC: positive analog input of channel 1, pin A I VADCG0.1 DS1NA AN2 AD14 I DS0PA AN3 I DS0NA AN4 AN5 I D / HighZ / Analog input 4 VDDM VADC analog input channel 4 of group 0 I D / HighZ / Analog input 5 VDDM VADC analog input channel 5 of group 0 I D / HighZ / Analog input 6 VDDM VADC analog input channel 6 of group 0 I D / HighZ / Analog input 7 VDDM VADC analog input channel 7 of group 0 (with pull down diagnostics) I D / HighZ / Analog input 8 VDDM VADC analog input channel 0 of group 1 I D / HighZ / Analog input 9 VDDM VADC analog input channel 1 of group 1 I D / HighZ / Analog input 10 VDDM VADC analog input channel 2 of group 1 I D / HighZ / Analog input 11 VDDM VADC analog input channel 3 of group 1 (with pull down diagnostics) I D / HighZ / Analog input 12 VDDM VADC analog input channel 4 of group 1 I D / HighZ / Analog input 13 VDDM VADC analog input channel 5 of group 1 I D / HighZ / Analog input 14 VDDM VADC analog input channel 6 of group 1 I D / HighZ / Analog input 15 VDDM VADC analog input channel 7 of group 1 VADCG0.5 AN6 AA13 VADCG0.6 AN7 AB13 VADCG0.7 AN8 AD13 VADCG1.0 AN9 AB12 VADCG1.1 AN10 AE13 VADCG1.2 AN11 AD12 VADCG1.3 AN12 AA12 VADCG1.4 AN13 AD11 VADCG1.5 AN14 AB11 VADCG1.6 AN15 AA11 VADCG1.7 Data Sheet D / HighZ / Analog input 3 VDDM VADC analog input channel 3 of group 0 DSADC: negative analog input channel 0, pin A VADCG0.4 AE14 D / HighZ / Analog input 2 VDDM VADC analog input channel 2 of group 0 DSADC: positive analog input of channel 0, pin A VADCG0.3 AA14 D / HighZ / Analog input 1 VDDM VADC analog input channel 1 of group 0 DSADC: negative analog input channel 1, pin A VADCG0.2 AB14 Function TOC-111 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-23 Analog Inputs (cont’d) Pin Symbol Ctrl Type AD10 AN16 I D / HighZ / Analog input 16 VDDM VADC analog input channel 0 of group 2 I D / HighZ / Analog input 17 VDDM VADC analog input channel 1 of group 2 I D / HighZ / Analog input 18 VDDM VADC analog input channel 2 of group 2 I D / HighZ / Analog input 19 VDDM VADC analog input channel 3 of group 2 (with pull down diagnostics) I D / HighZ / Analog input 20 VDDM VADC analog input channel 4 of group 2 VADCG2.0 AN17 AB10 VADCG2.1 AN18 AD9 VADCG2.2 AN19 AD8 VADCG2.3 AN20 AE8 VADCG2.4 Function DS2PA AN21 AE7 DSADC: positive analog input of channel 2, pin A I VADCG2.5 D / HighZ / Analog input 21 VDDM VADC analog input channel 5 of group 2 DS2NA AN22 AA10 DSADC: negative analog input channel 2, pin A I D / HighZ / Analog input 22 VDDM VADC analog input channel 6 of group 2 I D / HighZ / Analog input 23 VDDM VADC analog input channel 7 of group 2 I S/ HighZ / VDDM VADCG2.6 AN23 Y10 VADCG2.7 AN24 AD7 VADCG3.0 DS2PB SENT0A AN25 AD6 Analog input 24 VADC analog input channel 0 of group 3 DSADC: positive analog input of channel 2, pin B SENT input channel 0, pin A I VADCG3.1 S/ HighZ / VDDM Analog input 24 VADC analog input channel 1 of group 3 (with pull down diagnostics) DS2NB DSADC: negative analog input channel 2, pin B SENT1A SENT input channel 1, pin A AN26 AC7 I VADCG3.2 S/ HighZ / VDDM SENT2A AN27 AC6 I SENT3A AN28 VADCG3.4 Data Sheet VADC analog input channel 2 of group 3 (with pull down diagnostics) SENT input channel 2, pin A VADCG3.3 AB7 Analog input 26 S/ HighZ / VDDM Analog input 27 VADC analog input channel 3 of group 3 (with pull down diagnostics) SENT input channel 3, pin A I D / HighZ / Analog input 28 VDDM VADC analog input channel 4 of group 3 (with pull down diagnostics) TOC-112 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-23 Analog Inputs (cont’d) Pin Symbol Ctrl Type AB6 AN29 I D / HighZ / Analog input 29 VDDM VADC analog input channel 5 of group 3 (with pull down diagnostics) I D / HighZ / Analog input 30 VDDM VADC analog input channel 6 of group 3 I D / HighZ / Analog input 31 VDDM VADC analog input channel 7 of group 3 I S/ HighZ / VDDM VADCG3.5 AN30 AA9 VADCG3.6 AN31 Y9 VADCG3.7 AN32 W9 VADCG4.0 SENT4A AN33 Y6 I VADCG4.1 SENT5A AN34 W10 AN35 AN36 I S/ HighZ / VDDM SENT7A I DS3PB S/ HighZ / VDDM SENT8A I DS3NB SENT9A AN40 AN41 VADCG5.1 Data Sheet Analog input 37 VADC analog input channel 5 of group 4 DSADC: negative analog input channel 3, pin A Analog input 38 VADC analog input channel 6 of group 4 DSADC: positive analog input of channel 3, pin B S/ HighZ / VDDM Analog input 39 VADC analog input channel 7 of group 4 DSADC: negative analog input channel 3, pin B SENT input channel 9, pin A I D / HighZ / Analog input 40 VDDM VADC analog input channel 0 of group 5 I D / HighZ / Analog input 41 VDDM VADC analog input channel 1 of group 5 VADCG5.0 U9 DSADC: positive analog input of channel 3, pin A SENT input channel 8, pin A VADCG4.7 U10 VADC analog input channel 4 of group 4 SENT input channel 7, pin A VADCG4.6 AN39 Analog input 34 SENT input channel 6, pin A DS3NA W6 SENT input channel 5, pin A S/ HighZ / VDDM VADCG4.5 AN38 VADC analog input channel 1 of group 4 I SENT6A V10 Analog input 33 D / HighZ / Analog input 35 VDDM VADC analog input channel 3 of group 4 (with pull down diagnostics) DS3PA AN37 SENT input channel 4, pin A I VADCG4.4 W7 VADC analog input channel 0 of group 4 D / HighZ / Analog input 34 VDDM VADC analog input channel 2 of group 4 VADCG4.3 V9 S/ HighZ / VDDM Analog input 32 I VADCG4.2 Y7 Function TOC-113 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-23 Analog Inputs (cont’d) Pin Symbol Ctrl Type T10 AN42 I D / HighZ / Analog input 42 VDDM VADC analog input channel 2 of group 5 I D / HighZ / Analog input 43 VDDM VADC analog input channel 3 of group 5 (with pull down diagnostics) I D / HighZ / Analog input 44 VDDM VADC analog input channel 4 of group 5 VADCG5.2 AN43 T9 VADCG5.3 AN44 V6 VADCG5.4 DS3PC AN45 V7 DSADC: positive analog input of channel 3, pin C I VADCG5.5 DS3NC AN46 U6 I DS3PD AN47 I DS3ND AN48 AN49 I D / HighZ / Analog input 48 VDDM VADC analog input channel 0 of group 8 I D / HighZ / Analog input 49 VDDM VADC analog input channel 1 of group 8 (muxtest) I D / HighZ / Analog input 50 VDDM VADC analog input channel 2 of group 8 (muxtest) I D / HighZ / Analog input 51 VDDM VADC analog input channel 3 of group 8 I D / HighZ / Analog input 52 VDDM VADC analog input channel 4 of group 8 VADCG8.1 AN50 AJ6 VADCG8.2 AN51 AK6 VADCG8.3 AN52 AJ5 VADCG8.4 DS6PA AN53 AK5 DSADC: positive analog input of channel 6, pin A I VADCG8.5 DS6NA AN54 AJ4 I DS6PB AN55 I DS6NB AN56 VADCG9.0 Data Sheet D / HighZ / Analog input 5 VDDM VADC analog input channel 6 of group 8 DSADC: positive analog input of channel 6, pin B VADCG8.7 AF1 D / HighZ / Analog input 53 VDDM VADC analog input channel 5 of group 8 DSADC: negative analog input channel 6, pin A VADCG8.6 AK4 D / HighZ / Analog input 47 VDDM VADC analog input channel 7 of group 5 DSADC: negative analog input channel 3, pin D VADCG8.0 AJ7 D / HighZ / Analog input 46 VDDM VADC analog input channel 6 of group 5 DSADC: positive analog input of channel 3, pin D VADCG5.7 AK7 D / HighZ / Analog input 45 VDDM VADC analog input channel 5 of group 5 DSADC: negative analog input channel 3, pin C VADCG5.6 U7 Function D / HighZ / Analog input 50 VDDM VADC analog input channel 7 of group 8 DSADC: negative analog input channel 6, pin B I D / HighZ / Analog input 56 VDDM VADC analog input channel 0 of group 9 TOC-114 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-23 Analog Inputs (cont’d) Pin Symbol Ctrl Type AF2 AN57 I D / HighZ / Analog input 57 VDDM VADC analog input channel 1 of group 9 (muxtest) I D / HighZ / Analog input 58 VDDM VADC analog input channel 2 of group 9 (muxtest) I D / HighZ / Analog input 59 VDDM VADC analog input channel 3 of group 9 I D / HighZ / Analog input 60 VDDM VADC analog input channel 4 of group 9 VADCG9.1 AN58 AE2 VADCG9.2 AN59 AE1 VADCG9.3 AN60 AD1 VADCG9.4 Function DS7PA AN61 AD2 DSADC: positive analog input of channel 7, pin A I VADCG9.5 D / HighZ / Analog input 61 VDDM VADC analog input channel 5 of group 9 DS7NA AN62 AC2 DSADC: negative analog input channel 7, pin A I VADCG9.6 D / HighZ / Analog input 62 VDDM VADC analog input channel 6 of group 9 DS7PB AN63 AC1 DSADC: positive analog input of channel 7, pin B I VADCG9.7 D / HighZ / Analog input 63 VDDM VADC analog input channel 7 of group 9 DS7NB AN64 AB2 DSADC: negative analog input channel 7, pin B I D / HighZ / Analog input 64 VDDM VADC analog input channel 0 of group 10 I D / HighZ / Analog input 65 VDDM VADC analog input channel 1 of group 10 (muxtest) I D / HighZ / Analog input 66 VDDM VADC analog input channel 2 of group 10 (muxtest) VADCG10.0 AN65 AB1 VADCG10.1 AN66 AA2 VADCG10.2 DS8PB AN67 AA1 DSADC: positive analog input of channel 8, pin B I VADCG10.3 DS8NB S/ HighZ / VDDM SENT10A AN68 Y1 I DS8PA S/ HighZ / VDDM SENT11A AN69 VADCG10.5 DS8NA SENT12A Data Sheet VADC analog input channel 3 of group 10 DSADC: negative analog input channel 8, pin B SENT input channel 10, pin A VADCG10.4 Y2 Analog input 67 Analog input 68 VADC analog input channel 4 of group 10 DSADC: positive analog input of channel 8, pin A SENT input channel 11, pin A I S/ HighZ / VDDM Analog input 69 VADC analog input channel 5 of group 10 DSADC: negative analog input channel 8, pin A SENT input channel 12, pin A TOC-115 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-23 Analog Inputs (cont’d) Pin Symbol Ctrl Type Function W1 AN70 I S/ HighZ / VDDM Analog input 70 VADCG10.6 DS9PA SENT13A AN71 W2 VADC analog input channel 6 of group 10 DSADC: positive analog input of channel 9, pin A SENT input channel 13, pin A I VADCG10.7 DS9NA S/ HighZ / VDDM SENT14A Analog input 71 VADC analog input channel 7 of group 10 DSADC: negative analog input channel 9, pin A SENT input channel 14, pin A Table 2-24 System I/O Pin Symbol Ctrl Type Function M22 PORST I PORST / PD / VEXT Power On Reset Input Additional strong PD in case of power fail. L21 ESR0 I/O MP / OD / VEXT External System Request Reset 0 Default configuration during and after reset is opendrain driver. The driver drives low during power-on reset. This is valid additionally after deactivation of PORST until the internal reset phase has finished. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. EVRWUP ESR1 M21 EVRWUP I I/O EVR Wakeup Pin External System Request Reset 1 Default NMI function. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. MP / PU1 / VEXT I EVR Wakeup Pin AD22 VGATE1P O VGATE1P / -/ VEXT External Pass Device gate control for EVR13 AJ20 VGATE3P O VGATE3P / -/ VEXT External Pass Device gate control for EVR33 R21 TMS I A2 / PD / VDDP3 JTAG Module State Machine Control Input DAP1 T24 Data Sheet TRST I/O I A2 / PD / VDDP3 Device Access Port Line 1 JTAG Module Reset/Enable Input TOC-116 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-24 System I/O (cont’d) Pin Symbol Ctrl Type Function P21 TCK I JTAG Module Clock Input DAP0 I A2 / PD / VDDP3 Device Access Port Line 0 U25 XTAL1 I XTAL1 / -/ VDDP3 Main Oscillator/PLL/Clock Generator Input U24 XTAL2 O XTAL2 / -/ VDDP3 Main Oscillator/PLL/Clock Generator Output Table 2-25 Supply Pin Symbol Ctrl Type Function AE11 VAREF1 I Vx Positive Analog Reference Voltage 1 AE12 VAGND1 I Vx Negative Analog Reference Voltage 1 AA6 VAREF2 I Vx Positive Analog Reference Voltage 2 AA7 VAGND2 I Vx Negative Analog Reference Voltage 2 AE10, AJ9, AK9 VDDM I Vx ADC Analog Power Supply (3.3V / 5V) N12, M13 VDD / VDDSB I Vx Emulation Device: Emulation SRAM Standby Power Supply (1.3V) (Emulation Device only). Production Device: VDD (1.3V). M18, N19, V12, V19, W13, W18 VDD I Vx Digital Core Power Supply (1.3V) V24 VDD I Vx Digital Core Power Supply (1.3V). The supply pin inturn supplies the main XTAL Oscillator/PLL (1.3V) . A higher decoupling capacitor is therefore recommended to the VSS pin for better noise immunity. A2, B3, F7, G8, AC24, AD25, AH29, AJ30 VEXT I Vx External Power Supply (5V / 3.3V) A29, B28, F24, G23 VDDP3 I Vx Digital Power Supply for Flash (3.3V). Can be also used as external 3.3V Power Supply for VFLEX. V25 VDDP3 I Vx Digital Power Supply for Oscillator, LVDSH and A2 pads (3.3V). The supply pin inturn supplies the main XTAL Oscillator/PLL (3.3V) . A higher decoupling capacitor is therefore recommended to the VSS pin for better noise immunity. K20, J21 VDDFL3 I Vx Flash Power Supply (3.3V) J10 VFLEX I Vx Digital Power Supply for Flex Port Pads (5V / 3.3V) Data Sheet TOC-117 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-25 Supply (cont’d) Pin Symbol Ctrl Type Function AJ11, AK11, AK20, AK29 VFLEXE I Vx Digital Power Supply for EBU Flex Port Pads (5V / 3.3V) J29,J30, AH30 VEBU I Vx Digital Power Supply for EBU (3.3V) AK8, AJ8, AE9 VSSM I Vx Analog Ground for VDDM AA16 VEVRSB I Vx Standby Power Supply (3.3V/5V) for the Standby SRAM (CPU0.DSPR). If Standby mode is not used: To be handled like VEXT (3.3V/5V). A30, B2, B29, B30, F25, G7, VSS G24, H29, H30, J9, J22, K10, K21, T25, AA21, AB22, AD24, AE25, AJ10, AJ29, AK10, AK30 I Vx Digital Ground (outer balls) VSS I Vx Digital Ground (center balls) U12, U13, U15, U16, U18, U19 VSS I Vx Digital Ground (center balls) VSS I Vx Digital Ground (center balls) R13, R14, R15, R16, R17, R18 VSS I Vx Digital Ground (center balls) P12, P13, P15, P16, P18, P19 VSS I Vx Digital Ground (center balls) M14, M15, M16, M17, N14, N15, N16, N17 VSS I Vx Digital Ground (center balls) W15 VSS I Vx Digital Ground (center balls) This ball is used in the Emulation Device as AGBT TX0N W16 VSS I Vx Digital Ground (center balls) This ball is used in the Emulation Device as AGBT TX0P T12 VSS I Vx Digital Ground (center balls) This ball is used in the Emulation Device as AGBT CLKN R12 VSS I Vx Digital Ground (center balls) This ball is used in the Emulation Device as AGBT CLKP T19 VSS I Vx Digital Ground (center balls) This ball is used in the Emulation Device as AGBT ERR W14, W17, V14, V15, V16, V17 T13, T14, T15, T16, T17, T18 Data Sheet TOC-118 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: Table 2-25 Supply (cont’d) Pin Symbol NC AK2, AK3, AJ1, AJ2, AJ3, AH1, AH2, AG1, AG2, W30, V1, V2, V29, V30, T1, R1, R2, J1, H1, H2, G29, G30, F29, F30, E1, E2, E29, E30, D1, D2, D29, D30, C1, C2, C29, C30 B1, B4, B6, B9, B10, B14, B17, B20, B21, B25, B26, B27, A3, A4, A8, A9, A10, A17, A21, A25, A26, A27, A28 R19 NC / VDDPSB Ctrl Type Function I NC Not Connected. These pins are reserved for future extensions and shall not be connected externally. I NCVDD Emulation Device: Power Supply (3.3V) PSB for DAP/JTAG pad group. Can be connected to VDDP or can be left unsupplied (see document ´AurixED´ / Aurix Emulation Devices specification. Production Device: This pin is not connected on package level. It can be connected on PCB level to VDDP or Ground or can be left unsupplied. A1, F6, AK1, AE6, AB9 NC I NC1 Not Connected. These pins are not connected on package level and will not be used for future extensions. Legend: Column “Ctrl.”: I = Input (for GPIO port Lines with IOCR bit field Selection PCx = 0XXXB) O = Output O0 = Output with IOCR bit field selection PCx = 1X000B O1 = Output with IOCR bit field selection PCx = 1X001B (ALT1) O2 = Output with IOCR bit field selection PCx = 1X010B (ALT2) O3 = Output with IOCR bit field selection PCx = 1X011B (ALT3) O4 = Output with IOCR bit field selection PCx = 1X100B (ALT4) O5 = Output with IOCR bit field selection PCx = 1X101B (ALT5) O6 = Output with IOCR bit field selection PCx = 1X110B (ALT6) O7 = Output with IOCR bit field selection PCx = 1X111B (ALT7) Column “Type”: LP = Pad class LP (5V/3.3V, Class LP parameters for digital input / output and class D parameters for analog input function) MP = Pad class MP (5V/3.3V) MP+ = Pad class MP+ (5V/3.3V) MPR = Pad class MPR (5V/3.3V) A2 = Pad class A2 (3.3V) Data Sheet TOC-119 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: LVDSM = Pad class LVDSM (5V/3.3V) LVDSH = Pad class LVDSH (3.3V) S = Pad class S (Class S parameters for digital input and class D parameters for analog input function) D = Pad class D (VADC / DSADC) PU = with pull-up device connected during reset (PORST = 0) PU1 = with pull-up device connected during reset (PORST = 0)1) 2) 3) PD = with pull-down device connected during reset (PORST = 0) PD1 = with pull-down device connected during reset (PORST = 0)1) 2) 3) PX = Behavior depends on usage: PD in EVR13 SMPS Mode and PU1 in GPIO Mode OD = open drain during reset (PORST = 0) HighZ = tri-state during reset (PORST = 0) PORST = PORST input pad XTAL1 = XTAL1 input pad XTAL2 = XTAL2 input pad VGATE1P = VGATE1P VGATE3P = VGATE3P Vx = Supply NC = These pins are reserved for future extensions and shall not be connected externally NC1 = These pins are not connected on package level and will not be used for future extensions NCVDDPSB = This pin has a different functionality in an Production Device and an Emulation Device. For details pls. see Pin/Ball description of this pin. NCVDDSB = This pin has a different functionality in an Production Device and an Emulation Device. For details pls. see Pin/Ball description of this pin. 2.1.2 Emergency Stop Function The Emergency Stop function can be used to force GPIOs (General Purpose Inputs/Outputs) via an external input signal (EMGSTOPA or EMGSTOPB) into a defined state: • Input state and • PU or High-Z depending on HWCFG[6] level latched during Porst active Control of the Emergency Stop function: • The Emergency Stop function can be enabled/disabled in the SCU (see chapter “SCU”, “Emergency Stop Control”) • The Emergency Stop input signal, EMGSTOPA (P33.8) / EMGSTOPB (P21.2) , can selected in the SCU (see chapter “SCU”, “Emergency Stop Control”) • On port level, each GPIO can be enabled/disabled for the Emergency Stop function via the Px_ESR (Port x Emergency Stop) registers in the port control logic (see chapter “General Purpose I/O Ports and Peripheral I/O Lines”, “Emergency Stop Register”). The Emergency Stop function is available for all GPIO Ports with the following exceptions: • Not available for P20.2 (General Purpose Input/GPI only, overlayed with Testmode) • Not available for P40.x (analoge input ANx overlayed with GPI) • Not available for P32.0 EVR13 SMPS mode. 1) The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG[6] (P14.4). HWCFG[6] has a weak internal pull-up active at start-up if the pin is left unconnected.See also User´s Manual, “Introduction Chapter”, “General Purpose I/O Ports and Peripheral I/O Lines”, Figure: “Default state of port pins during and after reset”. 2) If HWCFG[6] is left unconnected or is externally pulled high, weak internal pull-ups (PU1) / pull-downs (PD1) are active during and after reset. 3) If HWCFG[6] is connected to ground, the PD1 / PU1 pins are predominantly in HighZ during and after reset. Data Sheet TOC-120 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC299x Pin Definition and Functions: • Not available for dedicated I/O without General Purpose Output function (e.g ESRx, TMS, TCK) The Emergency Stop function can be overruled on the following GPIO Ports: • P00.x and P02.x: Emergency Stop can be overruled by the 8-Bit Standby Controller (SBR), if implemented. Overruling can be disabled via the control registers P00_SCR / P02_SCR (see chapter “General Purpose I/O Ports and Peripheral I/O Lines”, P00 / P01) • P00.x: Emergency Stop can be overruled by the VADC. Overruling can be disabled via the control register P00_SCR (see chapter “General Purpose I/O Ports and Peripheral I/O Lines”, P00) • P14.0 and P14.1: Emergency Stop can be overruled in the DXCPL mode (DAP over can physical layer mode). No Overruling in the DXCM (Debug over can message) mode • P21.6: Emergency Stop can be overruled in JTAG mode if this pin is used as TDI • P21.7: Emergency Stop can be overruled in JTAG or Three Pin DAP mode • P20.0: Emergency Stop can be overruled in JTAG mode if this GPIO is used as TDI • P33.8: Emergency Stop can be overruled if this pin is used as safety output pin (SMUFSP) 2.1.3 Pull-Up/Pull-Down Reset Behavior of the Pins Table 2-26 List of Pull-Up/Pull-Down Reset Behavior of the Pins Pins PORST = 0 all GPIOs Pull-up if HWCFG[6] = 1 or High-Z if HWCFG[6] = 0 TDI, TESTMODE Pull-up 1) PORST Pull-down with IPORST relevant TRST, TCK, TMS Pull-down ESR0 The open-drain driver is used to drive low.2) ESR1 Pull-up3) TDO Pull-up 1) 2) 3) 4) PORST = 1 Pull-down with IPDLI relevant Pull-up3) High-Z/Pull-up4) Pull-down with IPORST relevant is always activated when a primary supply monitor detects a violation. Valid additionally after deactivation of PORST until the internal reset phase has finished. See the SCU chapter for details. See the SCU_IOCR register description. Depends on JTAG/DAP selection with TRST. In case of leakage test (PORST = 0 and TESTMODE = 0), the pull-down of the TRST pin is switched off. In case of an user application (TESTMODE = 1), the pull-down of the TRST is always switched on. Data Sheet TOC-121 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: 2.2 TC298x Pin Definition and Functions: BGA416 Figure 2-2 is showing the TC298x Logic Symbol for the package variant: BGA416. 1 4 5 6 7 8 9 10 17 18 19 20 21 22 23 24 25 26 P10.15 P10.11 2 3 P10.8 P11.3 P10.5 P10.2 P10.4 P10.0 P11.7 P12.0 P13.14 P13.10 P14.8 P14.12 P13.6 11 12 13 14 15 16 P13.5 VDDFL3 P14.11 P15.7 P15.4 ESR1 ESR0 P20.0 VEXT VSS A P10.7 A NC B P02.1 P02.0 P11.9 P10.9 P10.3 P10.1 P11.13 P11.5 P12.1 P13.12 P13.11 P14.15 P14.14 P13.7 P13.4 VDDFL3 P14.13 P15.6 P15.2 PORST P20.2 VEXT VSS VDD B C P02.4 P02.11 P10.14 P10.10 P11.12 P11.6 P11.15 P11.14 P11.8 P11.4 P11.1 P13.9 P14.6 P14.3 P14.10 P13.3 P13.0 P13.1 P14.9 P14.5 P14.0 P15.1 VEXT VSS VDD P21.5 C D P02.13 P02.15 P02.12 P02.5 VDD P11.2 P11.0 P14.7 P14.4 VEXT P13.2 P15.3 P15.5 P14.2 P14.1 VEXT VSS VDD P21.7 P21.4 D E P02.14 E VDD TCK P21.6 VDDP3 E F TRST TMS VSS VDD F G P21.3 P21.1 XTAL2 XTAL1 G H P21.2 VDDP3 VDDP3 VDDP3 H J P21.0 P22.1 P22.2 P22.3 J F G P01.0 P01.2 P10.13 P11.10 P11.11 VFLEX P02.2 P01.7 P02.9 E P02.3 P01.6 P02.10 F P10.6 P01.4 P01.5 G H P02.7 P02.6 P01.3 VDD H J P01.9 P01.1 P02.8 VSS J K P01.11 P01.10 P01.8 VEXT K L P01.15 P01.14 P01.13 P01.12 M P00.3 P00.2 P00.1 N P00.10 P00.9 P00.5 6 7 VSS 8 9 10 14 15 16 17 18 19 20 21 11 12 13 14 15 16 17 K VSS VSS VSS VSS VSS VSS VSS VSS K K P22.0 P23.4 P23.5 P23.6 K L L VSS VSS VSS VSS VSS VSS VSS VSS L L VSS P23.1 P23.2 P23.3 L P00.0 M M VSS VSS VSS VSS VSS VSS VSS VSS M M VEBU P24.14 P24.15 P23.0 M P00.4 N N VSS VSS VSS VSS VSS VSS VSS VSS N N P24.10 P24.11 P24.12 P24.13 N VSS VSS VSS VSS VSS VSS NC (VDDPSB) P P VDD P24.7 P24.8 P24.9 P VSS VSS VSS VSS VSS VSS (AGBT ERR) R R VSS P24.4 P24.5 P24.6 R P00.12 P00.11 P00.13 P00.15 P P R NC/ P00.14 VDDSB P00.8 13 10 P AN42 12 P15.8 Top-View VSS (AGBT CLKP) T 11 VSS P00.6 NC/ VDDSB R R VSS (AGBT CLKN) VSS P00.7 VSS T T VSS VSS VSS VSS VSS VSS VSS VSS T T VEBU P24.1 P24.2 P24.3 T VSS VSS VSS (AGBT TX0N) VSS (AGBT TX0P) VSS VSS VSS VSS U U P24.0 P25.13 P25.14 P25.15 U 10 11 12 13 14 15 16 17 V VDD P25.10 P25.11 P25.12 V U AN43 AN70 AN41 AN40 U U V AN71 AN68 AN37 AN36 V W AN69 AN64 AN32 VAREF2 W W VSS P25.7 P25.8 P25.9 W Y AN65 AN60 AN33 VAGND2 Y Y VEBU P25.3 P25.4 P25.5 Y AA AN61 AN26 AN5 AN56 AA AA P25.2 P25.1 P26.0 P25.0 AA AB AN28 AN27 AN57 AN7 AB AB VDD P30.2 P30.7 P30.12 AB AC AN29 AN4 AN16 AN8 AN0 VSS P30.3 P30.8 P30.13 AC AD AN6 AN48 AN17 AN9 AN1 AE AN49 AN18 AN10 AN2 VDDM AN52 AN54 AN22 VDDM AF NC AN19 AN11 AN3 VSSM AN53 AN55 AN23 1 2 3 4 5 6 7 8 6 7 8 9 10 11 12 13 19 20 VAGND1 AN24 AN20 P34.1 P34.2 P33.0 P33.4 P33.14 P32.4 P33.7 VEXT VGATE1P VFLEXE VSS VDD VAREF1 AN25 AN21 VEVRSB P34.4 P33.1 P33.5 P33.15 P32.5 P33.8 VEXT P32.0 P31.0 P31.3 P31.6 P31.9 P31.12 P31.14 P30.4 P30.9 P30.14 AD P34.5 P33.2 P33.6 P32.2 P33.10 P33.13 VEXT P32.6 P31.1 P31.4 P31.7 P31.10 P31.13 P31.15 P30.5 P30.10 P30.15 AE VSSM P34.3 9 10 P33.3 P33.9 P32.3 P33.11 P33.12 VEXT P32.7 P31.2 P31.5 P31.8 P31.11 P30.0 P30.1 P30.6 P30.11 NC AF 11 12 16 17 18 19 20 21 22 23 24 25 26 13 14 14 15 15 16 17 18 21 VGATE3P VFLEXE Figure 2-2 TC298x Logic Symbol for the package variant BGA416. Data Sheet TOC-122 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: 2.2.1 TC298x BGA416 Package Variant Pin Configuration Table 2-27 Port 00 Functions Pin Symbol Ctrl Type Function M4 P00.0 I MP / PU1 / VEXT General-purpose input TIN9 CTRAPA GTM input CCU61 input T12HRE CCU60 input INJ00 MSC0 input CIFD9 CIF input P00.0 O0 General-purpose output TOUT9 O1 GTM output ASCLK3 O2 ASCLIN3 output ATX3 O3 ASCLIN3 output – O4 Reserved TXDCAN1 O5 CAN node 1 output – O6 Reserved COUT63 O7 CCU60 output ETHMDIOA HWOU T ETH input/output Data Sheet TOC-123 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-27 Port 00 Functions (cont’d) Pin Symbol Ctrl Type Function M3 P00.1 I LP / PU1 / VEXT General-purpose input TIN10 ARX3E M2 GTM input ASCLIN3 input RXDCAN1D CAN node 1 input PSIRX0A PSI5 input SENT0B SENT input CC60INB CCU60 input CC60INA CCU61 input DSCIN5A DSADC channel 5 input DS5NA DSADC positive analog input of channel channel 5, pin A DSCIN7B DSADC channel 7 input VADCG7.5 VADC analog input channel 5 of group 7 CIFD10 CIF input P00.1 O0 General-purpose output TOUT10 O1 GTM output ATX3 O2 ASCLIN3 output – O3 Reserved DSCOUT5 O4 DSADC channel 5 output DSCOUT7 O5 DSADC channel 7 output SPC0 O6 SENT output CC60 O7 CCU61 output P00.2 I TIN11 SENT1B LP / PU1 / VEXT General-purpose input GTM input SENT input DSDIN5A DSADC channel 5 input DSDIN7B DSADC channel 7 input DS5PA DSADC negative analog input of channel 5, pin A VADCG7.4 VADC analog input channel 4 of group 7 CIFD11 CIF input P00.2 O0 General-purpose output TOUT11 O1 GTM output ASCLK3 O2 ASCLIN3 output TXDCANr1 O3 CAN node 1 output (MultiCANr+) PSITX0 O4 PSI5 output TXDCAN3 O5 CAN node 3 output SLSO34 O6 QSPI3 output COUT60 O7 CCU61 output Data Sheet TOC-124 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-27 Port 00 Functions (cont’d) Pin Symbol Ctrl Type Function M1 P00.3 I LP / PU1 / VEXT General-purpose input TIN12 RXDCAN3A N4 GTM input CAN node 3 input RXDCANr1A CAN node 1 input (MultiCANr+) PSIRX1A PSI5 input PSISRXA PSI5-S input SENT2B SENT input CC61INB CCU60 input CC61INA CCU61 input DSCIN3A DSADC channel 3 input VADCG7.3 VADC analog input channel 3 of group 7 DSITR5F DSADC channel 5 input CIFD12 CIF input P00.3 O0 General-purpose output TOUT12 O1 GTM output ASLSO3 O2 ASCLIN3 output – O3 Reserved DSCOUT3 O4 DSADC channel 3 output – O5 Reserved SPC2 O6 SENT output CC61 O7 CCU61 output P00.4 I TIN13 REQ7 LP / PU1 / VEXT General-purpose input GTM input SCU input SENT3B SENT input DSDIN3A DSADC channel 3 input DSSGNA DSADC channel input VADCG7.2 VADC analog input channel 2 of group 7 CIFD13 CIF input P00.4 O0 General-purpose output TOUT13 O1 GTM output PSISTX O2 PSI5-S output – O3 Reserved PSITX1 O4 PSI5 output VADCG4BFL0 O5 VADC output SPC3 O6 SENT output COUT61 O7 CCU61 output Data Sheet TOC-125 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-27 Port 00 Functions (cont’d) Pin Symbol Ctrl Type Function N3 P00.5 I LP / PU1 / VEXT General-purpose input TIN14 PSIRX2A R3 GTM input PSI5 input SENT4B SENT input CC62INB CCU60 input CC62INA CCU61 input DSCIN2A DSADC channel 2 input VADCG7.1 VADC analog input channel 1 of group 7 CIFD14 CIF input P00.5 O0 General-purpose output TOUT14 O1 GTM output DSCGPWMN O2 DSADC output SLSO33 O3 QSPI3 output DSCOUT2 O4 DSADC channel 2 output VADCG4BFL1 O5 VADC output SPC4 O6 SENT output CC62 O7 CCU61 output P00.6 I TIN15 SENT5B LP / PU1 / VEXT General-purpose input GTM input SENT input DSDIN2A DSADC channel 2 input A VADCG7.0 VADC analog input channel 0 of group 7 (with pull down diagnostics) DSITR4F DSADC channel 4 input F CIFD15 CIF input P00.6 O0 General-purpose output TOUT15 O1 GTM output DSCGPWMP O2 DSADC output VADCG4BFL2 O3 VADC output PSITX2 O4 PSI5 output VADCEMUX10 O5 VADC output SPC5 O6 SENT output COUT62 O7 CCU61 output Data Sheet TOC-126 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-27 Port 00 Functions (cont’d) Pin Symbol Ctrl Type Function T3 P00.7 I LP / PU1 / VEXT General-purpose input TIN16 SENT6B T2 GTM input SENT input CC60INC CCU61 input CCPOS0A CCU61 input T12HRB CCU60 input T2INA GPT120 input DSCIN4A DSADC channel 4 input A DS4NA DSADC negative analog input channel 4, pin A VADCG6.5 VADC analog input channel 5 of group 6 CIFCLK CIF input P00.7 O0 General-purpose output TOUT16 O1 GTM output – O2 Reserved VADCG4BFL3 O3 VADC output DSCOUT4 O4 DSADC channel 4 output VADCEMUX11 O5 VADC output SPC6 O6 SENT output CC60 O7 CCU61 output P00.8 I TIN17 SENT7B LP / PU1 / VEXT General-purpose input GTM input SENT input CC61INC CCU61 input CCPOS1A CCU61 input T13HRB CCU60 input T2EUDA GPT120 input DSDIN4A DSADC channel 4 input A DS4PA DSADC positive analog input of channel 4, pin A VADCG6.4 VADC analog input channel 4 of group 6 CIFVSNC CIF input P00.8 O0 General-purpose output TOUT17 O1 GTM output SLSO36 O2 QSPI3 output – O3 Reserved – O4 Reserved VADCEMUX12 O5 VADC output SPC7 O6 SENT output CC61 O7 CCU61 output Data Sheet TOC-127 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-27 Port 00 Functions (cont’d) Pin Symbol Ctrl Type Function N2 P00.9 I LP / PU1 / VEXT General-purpose input TIN18 SENT8B N1 GTM input SENT input CC62INC CCU61 input CCPOS2A CCU61 input T13HRC CCU60 input T12HRC CCU60 input T4EUDA GPT120 input DSCIN1A DSADC channel 1 input A VADCG6.3 VADC analog input channel 3 of group 6 DSITR3F DSADC channel 3 input F CIFHSNC CIF input P00.9 O0 General-purpose output TOUT18 O1 GTM output SLSO37 O2 QSPI3 output ARTS3 O3 ASCLIN3 output DSCOUT1 O4 DSADC channel 1 output – O5 Reserved SPC8 O6 SENT output CC62 O7 CCU61 output P00.10 I TIN19 SENT9B LP / PU1 / VEXT General-purpose input GTM input SENT input DSDIN1A DSADC channel 1 input A VADCG6.2 VADC analog input channel 2 of group 6 P00.10 O0 General-purpose output TOUT19 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved SPC9 O6 SENT output COUT63 O7 CCU61 output Data Sheet TOC-128 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-27 Port 00 Functions (cont’d) Pin Symbol Ctrl Type Function P2 P00.11 I LP / PU1 / VEXT General-purpose input TIN20 CTRAPA P1 CCU60 input T12HRE CCU61 input DSCIN0A DSADC channel 0 input A VADCG6.1 VADC analog input channel 1 of group 6 P00.11 O0 General-purpose output TOUT20 O1 GTM output – O2 Reserved – O3 Reserved DSCOUT0 O4 DSADC channel 0 output – O5 Reserved – O6 Reserved – O7 Reserved P00.12 I TIN21 ACTS3A P3 GTM input LP / PU1 / VEXT General-purpose input GTM input ASCLIN3 input DSDIN0A DSADC channel 0 input A VADCG6.0 VADC analog input channel 0 of group 6 P00.12 O0 General-purpose output TOUT21 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved COUT63 O7 CCU61 output P00.13 I TIN167 DSDIN6A MP+ / PU1 / VEXT General-purpose input GTM input DSADC channel 6 input A P00.13 O0 General-purpose output TOUT167 O1 GTM output – O2 Reserved – O3 Reserved EXTCLK1 O4 SCU output – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-129 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-27 Port 00 Functions (cont’d) Pin Symbol Ctrl Type Function R2 P00.14 I LP / PU1 / VEXT General-purpose input TIN166 DSCIN6A P4 GTM input DSADC channel 6 input A P00.14 O0 General-purpose output TOUT166 O1 GTM output – O2 Reserved – O3 Reserved DSCOUT6 O4 DSADC channel 6 output – O5 Reserved – O6 Reserved – O7 Reserved P00.15 I MP+ / PU1 / VEXT TIN168 DSITR6F General-purpose input GTM input DSADC channel 6 input F P00.15 O0 General-purpose output TOUT168 O1 GTM output – O2 Reserved – O3 Reserved EXTCLK0 O4 SCU output – O5 Reserved – O6 Reserved – O7 Reserved Table 2-28 Port 01 Functions Pin Symbol Ctrl Type Function F1 P01.0 I LP / PU1 / VEXT General-purpose input TIN155 DSITR6E GTM input DSADC channel 6 input E RXDCAN3F CAN node 3 input RXDCANr1E CAN node 1 input (MultiCANr+) P01.0 O0 General-purpose output TOUT155 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-130 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-28 Port 01 Functions (cont’d) Pin Symbol Ctrl Type Function J2 P01.1 I LP / PU1 / VEXT General-purpose input TIN159 DSITR8E G1 DSADC channel 8 input E RXD1A1 ERAY1 input SENT10B SENT input P01.1 O0 General-purpose output TOUT159 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P01.2 I TIN156 DSCIN7A H3 GTM input LP / PU1 / VEXT General-purpose input GTM input DSADC channel 7 input A P01.2 O0 General-purpose output TOUT156 O1 GTM output – O2 Reserved TXDCAN3 O3 CAN node 3 output – O4 Reserved TXDCANr1 O5 CAN node 1 output (MultiCANr+) DSCOUT7 O6 DSADC channel 7 output – O7 Reserved P01.3 I TIN111 SLSI3B DSITR7F LP / PU1 / VEXT General-purpose input GTM input QSPI3 input DSADC channel 7 input F P01.3 O0 General-purpose output TOUT111 O1 GTM output – O2 Reserved – O3 Reserved SLSO39 O4 QSPI3 output TXDCAN1 O5 CAN node 1 output – O6 Reserved – O7 Reserved Data Sheet TOC-131 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-28 Port 01 Functions (cont’d) Pin Symbol Ctrl Type Function G3 P01.4 I LP / PU1 / VEXT General-purpose input TIN112 RXDCAN1C DSITR7E G4 CAN node 1 input DSADC channel 7 input E P01.4 O0 General-purpose output TOUT112 O1 GTM output – O2 Reserved – O3 Reserved SLSO310 O4 QSPI3 output – O5 Reserved – O6 Reserved – O7 Reserved P01.5 I TIN113 MRST3C LP / PU1 / VEXT DSCIN8A F3 GTM input General-purpose input GTM input QSPI3 input DSADC channel 8 input A P01.5 O0 General-purpose output TOUT113 O1 GTM output – O2 Reserved – O3 Reserved MRST3 O4 QSPI3 output – O5 Reserved DSCOUT8 O6 DSADC channel 8 output – O7 Reserved P01.6 I TIN114 MTSR3C DSDIN8A MP / PU1 / VEXT General-purpose input GTM input QSPI3 input DSADC channel 8 input A P01.6 O0 General-purpose output TOUT114 O1 GTM output – O2 Reserved – O3 Reserved MTSR3 O4 QSPI3 output – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-132 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-28 Port 01 Functions (cont’d) Pin Symbol Ctrl Type Function E3 P01.7 I MP / PU1 / VEXT General-purpose input TIN115 SCLK3C DSITR8F K3 GTM input QSPI3 input DSADC channel 8 input F P01.7 O0 General-purpose output TOUT115 O1 GTM output – O2 Reserved – O3 Reserved SCLK3 O4 QSPI3 output – O5 Reserved – O6 Reserved – O7 Reserved P01.8 I TIN162 DSDIN9A LP / PU1 / VEXT General-purpose input GTM input DSADC channel 9 input A SENT12B SENT input ARX0C ASCLIN0 input RXDCAN0F CAN node 0 input RXDCANr0E CAN node 0 input (MultiCANr+) RXD1B1 ERAY1 input P01.8 O0 General-purpose output TOUT162 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-133 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-28 Port 01 Functions (cont’d) Pin Symbol Ctrl Type Function J1 P01.9 I LP / PU1 / VEXT General-purpose input TIN160 DSCIN9A SENT11B K2 DSADC channel 9 input A SENT input P01.9 O0 General-purpose output TOUT160 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved DSCOUT9 O6 DSADC channel 9 output – O7 Reserved P01.10 I TIN163 DSITR9F LP / PU1 / VEXT SENT13B K1 GTM input General-purpose input GTM input DSADC channel 9 input F SENT input P01.10 O0 General-purpose output TOUT163 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P01.11 I TIN165 DSITR9E SENT14B LP / PU1 / VEXT General-purpose input GTM input DSADC channel 9 input E SENT input P01.11 O0 General-purpose output TOUT165 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-134 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-28 Port 01 Functions (cont’d) Pin Symbol Ctrl Type Function L4 P01.12 I MP+ / PU1 / VEXT General-purpose input TIN158 L3 P01.12 O0 TOUT158 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved TXD1A O6 ERAY1 output – O7 Reserved P01.13 I TIN161 L2 GTM input MP+ / PU1 / VEXT General-purpose output General-purpose input GTM input P01.13 O0 TOUT161 O1 GTM output ATX0 O2 ASCLIN0 output – O3 Reserved TXDCAN0 O4 CAN node 0 output TXDCANr0 O5 CAN node 0 output (MultiCANr+) TXD1B O6 ERAY1 output – O7 Reserved P01.14 I TIN164 MP+ / PU1 / VEXT General-purpose output General-purpose input GTM input P01.14 O0 TOUT164 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved TXEN1A O6 ERAY1 output – O7 Reserved Data Sheet General-purpose output TOC-135 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-28 Port 01 Functions (cont’d) Pin Symbol Ctrl Type Function L1 P01.15 I LP / PU1 / VEXT General-purpose input TIN157 DSDIN7A GTM input DSADC channel 7 input A P01.15 O0 General-purpose output TOUT157 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Table 2-29 Port 02 Functions Pin Symbol Ctrl Type Function B2 P02.0 I MP+ / PU1 / VEXT General-purpose input TIN0 REQ6 GTM input SCU input ARX2G ASCLIN2 input CC60INA CCU60 input CC60INB CCU61 input CIFD0 CIF input P02.0 O0 General-purpose output TOUT0 O1 GTM output ATX2 O2 ASCLIN2 output SLSO31 O3 QSPI3 output DSCGPWMN O4 DSADC output TXDCAN0 O5 CAN node 0 output TXD0A O6 ERAY0 output CC60 O7 CCU60 output Data Sheet TOC-136 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-29 Port 02 Functions (cont’d) Pin Symbol Ctrl Type B1 P02.1 I LP / PU1 General-purpose input / VEXT GTM input TIN1 E2 Function REQ14 SCU input ARX2B ASCLIN2 input RXDCAN0A CAN node 0 input RXD0A2 ERAY0 input CIFD1 CIF input P02.1 O0 General-purpose output TOUT1 O1 GTM output SLSO47 O2 QSPI4 output SLSO32 O3 QSPI3 output DSCGPWMP O4 DSADC output – O5 Reserved – O6 Reserved COUT60 O7 CCU60 output P02.2 I TIN2 CC61INA MP+ / PU1 / VEXT General-purpose input GTM input CCU60 input CC61INB CCU61 input CIFD2 CIF input P02.2 O0 General-purpose output TOUT2 O1 GTM output ATX1 O2 ASCLIN1 output SLSO33 O3 QSPI3 output PSITX0 O4 PSI5 output TXDCAN2 O5 CAN node 2 output TXD0B O6 ERAY0 output CC61 O7 CCU60 output Data Sheet TOC-137 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-29 Port 02 Functions (cont’d) Pin Symbol Ctrl Type Function F2 P02.3 I LP / PU1 / VEXT General-purpose input TIN3 ARX1G C1 GTM input ASCLIN1 input RXDCAN2B CAN node 2 input RXD0B2 ERAY0 input PSIRX0B PSI5 input DSCIN5B DSADC channel 5 input B SDI11 MSC1 input CIFD3 CIF input P02.3 O0 General-purpose output TOUT3 O1 GTM output ASLSO2 O2 ASCLIN2 output SLSO34 O3 QSPI3 output DSCOUT5 O4 DSADC channel 5 output – O5 Reserved – O6 Reserved COUT61 O7 CCU60 output P02.4 I TIN4 SLSI3A MP+ / PU1 / VEXT General-purpose input GTM input QSPI3 input ECTT1 TTCAN input RXDCAN0D CAN node 0 input CC62INA CCU60 input CC62INB CCU61 input DSDIN5B DSADC channel 5 input B SDA0A I2C0 input CIFD4 CIF input P02.4 O0 General-purpose output TOUT4 O1 GTM output ASCLK2 O2 ASCLIN2 output SLSO30 O3 QSPI3 output PSISCLK O4 PSI5-S output SDA0 O5 I2C0 output TXEN0A O6 ERAY0 output CC62 O7 CCU60 output Data Sheet TOC-138 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-29 Port 02 Functions (cont’d) Pin Symbol Ctrl Type Function D4 P02.5 I MP+ / PU1 / VEXT General-purpose input TIN5 MRST3A H2 GTM input QSPI3 input ECTT2 TTCAN input PSIRX1B PSI5 input PSISRXB PSI5-S input SENT3C SENT input DSCIN4B DSADC channel 4 input B SCL0A I2C0 input CIFD5 CIF input P02.5 O0 General-purpose output TOUT5 O1 GTM output TXDCAN0 O2 CAN node 0 output MRST3 O3 QSPI3 output DSCOUT4 O4 DSADC channel 4 output SCL0 O5 I2C0 output TXEN0B O6 ERAY0 output COUT62 O7 CCU60 output P02.6 I TIN6 MTSR3A MP / PU1 / VEXT General-purpose input GTM input QSPI3 input SENT2C SENT input CC60INC CCU60 input CCPOS0A CCU60 input T12HRB CCU61 input T3INA GPT120 input CIFD6 CIF input DSDIN4B DSADC channel 4 input B DSITR5E DSADC channel 5 input E P02.6 O0 General-purpose output TOUT6 O1 GTM output PSISTX O2 PSI5-S output MTSR3 O3 QSPI3 output PSITX1 O4 PSI5 output VADCEMUX00 O5 VADC output – O6 Reserved CC60 O7 CCU60 output Data Sheet TOC-139 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-29 Port 02 Functions (cont’d) Pin Symbol Ctrl Type Function H1 P02.7 I MP / PU1 / VEXT General-purpose input TIN7 SCLK3A GTM input QSPI3 input PSIRX2B PSI5 input SENT1C SENT input CC61INC CCU60 input CCPOS1A CCU60 input T13HRB CCU61 input T3EUDA GPT120 input CIFD7 CIF input DSCIN3B DSADC channel 3 input B DSITR4E DSADC channel 4 input E P02.7 O0 General-purpose output TOUT7 O1 GTM output – O2 Reserved SCLK3 O3 QSPI3 output DSCOUT3 O4 DSADC channel 3 output VADCEMUX01 O5 VADC output SPC1 O6 SENT output CC61 O7 CCU60 output Data Sheet TOC-140 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-29 Port 02 Functions (cont’d) Pin Symbol Ctrl Type J3 P02.8 I SENT0C LP / PU1 General-purpose input / GTM input VEXT SENT input CC62INC CCU60 input CCPOS2A CCU60 input T12HRC CCU61 input T13HRC CCU61 input T4INA GPT120 input CIFD8 CIF input DSDIN3B DSADC channel 3 input B DSITR3E DSADC channel 3 input E TIN8 E4 Function P02.8 O0 General-purpose output TOUT8 O1 GTM output SLSO35 O2 QSPI3 output – O3 Reserved PSITX2 O4 PSI5 output VADCEMUX02 O5 VADC output ETHMDC O6 ETH output CC62 O7 CCU60 output P02.9 I TIN116 LP / PU1 / VEXT General-purpose input GTM input P02.9 O0 TOUT116 O1 GTM output ATX2 O2 ASCLIN2 output – O3 Reserved – O4 Reserved TXDCAN1 O5 CAN node 1 output – O6 Reserved – O7 Reserved Data Sheet General-purpose output TOC-141 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-29 Port 02 Functions (cont’d) Pin Symbol Ctrl Type Function F4 P02.10 I LP / PU1 / VEXT General-purpose input TIN117 ARX2C RXDCAN1E C2 ASCLIN2 input CAN node 1 input P02.10 O0 General-purpose output TOUT117 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P02.11 I TIN118 D3 GTM input LP / PU1 / VEXT General-purpose input GTM input P02.11 O0 TOUT118 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P02.12 I TIN151 LP / PU1 / VEXT General-purpose output General-purpose input GTM input P02.12 O0 TOUT151 O1 GTM output SLSO35 O2 QSPI3 output SLSO44 O3 QSPI4 output – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet General-purpose output TOC-142 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-29 Port 02 Functions (cont’d) Pin Symbol Ctrl Type Function D1 P02.13 I LP / PU1 / VEXT General-purpose input TIN153 E1 P02.13 O0 TOUT153 O1 GTM output SLSO37 O2 QSPI3 output SLSO46 O3 QSPI4 output TXDCAN0 O4 CAN node 0 output TXDCANr0 O5 CAN node 0 output (MultiCANr+) – O6 Reserved – O7 Reserved P02.14 I TIN154 RXDCAN0H LP / PU1 / VEXT RXDCANr0D D2 GTM input General-purpose output General-purpose input GTM input CAN node 0 input CAN node 0 input (MultiCANr+) P02.14 O0 General-purpose output TOUT154 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P02.15 I TIN152 MP+ / PU1 / VEXT General-purpose input GTM input P02.15 O0 TOUT152 O1 GTM output SLSO36 O2 QSPI3 output SLSO45 O3 QSPI4 output – O4 Reserved – O5 Reserved TXEN1B O6 ERAY1 output – O7 Reserved Data Sheet General-purpose output TOC-143 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-30 Port 10 Functions Pin Symbol Ctrl Type Function A9 P10.0 I LP / PU1 / VEXT General-purpose input TIN102 T6EUDB B8 GPT120 input P10.0 O0 General-purpose output TOUT102 O1 GTM output – O2 Reserved SLSO110 O3 QSPI1 output – O4 Reserved VADCG6BFL0 O5 VADC output – O6 Reserved – O7 Reserved P10.1 I TIN103 MRST1A MP+ / PU1 / VEXT T5EUDB A7 GTM input General-purpose input GTM input QSPI1 input GPT120 input P10.1 O0 General-purpose output TOUT103 O1 GTM output MTSR1 O2 QSPI1 output MRST1 O3 QSPI1 output EN01 O4 MSC0 output VADCG6BFL1 O5 VADC output END03 O6 MSC0 output – O7 Reserved P10.2 I TIN104 SCLK1A MP / PU1 / VEXT General-purpose input GTM input QSPI1 input T6INB GPT120 input REQ2 SCU input RXDCAN2E CAN node 2 input SDI01 MSC0 input P10.2 O0 General-purpose output TOUT104 O1 GTM output – O2 Reserved SCLK1 O3 QSPI1 output EN00 O4 MSC0 output VADCG6BFL2 O5 VADC output END02 O6 MSC0 output – O7 Reserved Data Sheet TOC-144 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-30 Port 10 Functions (cont’d) Pin Symbol Ctrl Type Function B7 P10.3 I MP / PU1 / VEXT General-purpose input TIN105 MTSR1A A8 GTM input QSPI1 input REQ3 SCU input T5INB GPT120 input P10.3 O0 General-purpose output TOUT105 O1 GTM output VADCG6BFL3 O2 VADC output MTSR1 O3 QSPI1 output EN00 O4 MSC0 output END02 O5 MSC0 output TXDCAN2 O6 CAN node 2 output – O7 Reserved P10.4 I TIN106 MTSR1C MP+ / PU1 / VEXT General-purpose input GTM input QSPI1 input CCPOS0C CCU60 input T3INB GPT120 input P10.4 O0 General-purpose output TOUT106 O1 GTM output – O2 Reserved SLSO18 O3 QSPI1 output MTSR1 O4 QSPI1 output EN00 O5 MSC0 output END02 O6 MSC0 output – O7 Reserved Data Sheet TOC-145 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-30 Port 10 Functions (cont’d) Pin Symbol Ctrl Type Function A6 P10.5 I LP / PU1 / VEXT General-purpose input TIN107 HWCFG4 G2 GTM input SCU input RXDCANr0A CAN node 0 input (MultiCANr+) INJ01 MSC0 input P10.5 O0 General-purpose output TOUT107 O1 GTM output ATX2 O2 ASCLIN2 output SLSO38 O3 QSPI3 output SLSO19 O4 QSPI1 output T6OUT O5 GPT120 output ASLSO2 O6 ASCLIN2 output PSITX3 O7 PSI5 output P10.6 I TIN108 ARX2D LP / PU1 / VEXT General-purpose input GTM input ASCLIN2 input MTSR3B QSPI3 input PSIRX3C PSI5 input HWCFG5 SCU input P10.6 O0 General-purpose output TOUT108 O1 GTM output ASCLK2 O2 ASCLIN2 output MTSR3 O3 QSPI3 output T3OUT O4 GPT120 output TXDCANr0 O5 CAN node 0 output (MultiCANr+) MRST1 O6 QSPI1 output VADCG7BFL0 O7 VADC output Data Sheet TOC-146 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-30 Port 10 Functions (cont’d) Pin Symbol Ctrl Type Function B4 P10.7 I LP / PU1 / VEXT General-purpose input TIN109 ACTS2A A4 GTM input ASCLIN2 input MRST3B QSPI3 input REQ4 SCU input CCPOS1C CCU60 input T3EUDB GPT120 input P10.7 O0 General-purpose output TOUT109 O1 GTM output – O2 Reserved MRST3 O3 QSPI3 output VADCG7BFL1 O4 VADC output TXDCANr0 O5 CAN node 0 output (MultiCANr+) – O6 Reserved – O7 Reserved P10.8 I TIN110 SCLK3B LP / PU1 / VEXT General-purpose input GTM input QSPI3 input REQ5 SCU input CCPOS2C CCU60 input T4INB GPT120 input RXDCANr0B CAN node 0 input (MultiCANr+) P10.8 O0 General-purpose output TOUT110 O1 GTM output ARTS2 O2 ASCLIN2 output SCLK3 O3 QSPI3 output – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-147 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-30 Port 10 Functions (cont’d) Pin Symbol Ctrl Type Function B6 P10.9 I LP / PU1 / VEXT General-purpose input TIN265 SENT10C C4 SENT input P10.9 O0 General-purpose output TOUT265 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P10.10 I TIN266 SENT11C A3 GTM input LP / PU1 / VEXT General-purpose input GTM input SENT input P10.10 O0 General-purpose output TOUT266 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P10.11 I TIN269 SENT14C LP / PU1 / VEXT General-purpose input GTM input SENT input P10.11 O0 General-purpose output TOUT269 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-148 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-30 Port 10 Functions (cont’d) Pin Symbol Ctrl Type Function B3 P10.13 I LP / PU1 / VEXT General-purpose input TIN268 SENT13C C3 SENT input P10.13 O0 General-purpose output TOUT268 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P10.14 I TIN267 SENT12C A2 GTM input LP / PU1 / VEXT General-purpose input GTM input SENT input P10.14 O0 General-purpose output TOUT267 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P10.15 I TIN270 LP / PU1 / VEXT General-purpose input GTM input P10.15 O0 TOUT270 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet General-purpose output TOC-149 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-31 Port 11 Functions Pin Symbol Ctrl Type Function D11 P11.0 I MP+ / PU1 / VFLEX General-purpose input TIN119 ARX3B C11 ASCLIN3 input P11.0 O0 General-purpose output TOUT119 O1 GTM output ATX3 O2 ASCLIN3 output – O3 Reserved – O4 Reserved – O5 Reserved ETHTXD3 O6 ETH output – O7 Reserved P11.1 I TIN120 D10 GTM input MP+ / PU1 / VFLEX General-purpose input GTM input P11.1 O0 TOUT120 O1 GTM output ASCLK3 O2 ASCLIN3 output ATX3 O3 ASCLIN3 output – O4 Reserved – O5 Reserved ETHTXD2 O6 ETH output – O7 Reserved P11.2 I TIN95 MPR/ PU1 / VFLEX General-purpose output General-purpose input GTM input P11.2 O0 TOUT95 O1 GTM output END03 O2 MSC0 output SLSO05 O3 QSPI0 output SLSO15 O4 QSPI1 output EN01 O5 MSC0 output ETHTXD1 O6 ETH output COUT63 O7 CCU60 output Data Sheet General-purpose output TOC-150 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-31 Port 11 Functions (cont’d) Pin Symbol Ctrl Type Function A5 P11.3 I MPR / PU1 / VFLEX General-purpose input TIN96 MRST1B SDI03 C10 QSPI1 input MSC0 input P11.3 O0 General-purpose output TOUT96 O1 GTM output – O2 Reserved MRST1 O3 QSPI1 output TXD0A O4 ERAY0 output – O5 Reserved ETHTXD0 O6 ETH output COUT62 O7 CCU60 output P11.4 I TIN121 ETHRXCLKB B10 GTM input MP+ / PU1 / VFLEX General-purpose input GTM input ETH input P11.4 O0 General-purpose output TOUT121 O1 GTM output ASCLK3 O2 ASCLIN3 output – O3 Reserved – O4 Reserved – O5 Reserved ETHTXER O6 ETH output – O7 Reserved P11.5 I TIN122 ETHTXCLKA LP / PU1 / VFLEX General-purpose input GTM input ETH input P11.5 O0 General-purpose output TOUT122 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-151 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-31 Port 11 Functions (cont’d) Pin Symbol Ctrl Type Function C6 P11.6 I MPR / PU1 / VFLEX General-purpose input TIN97 SCLK1B A10 QSPI1 input P11.6 O0 General-purpose output TOUT97 O1 GTM output TXEN0B O2 ERAY0 output SCLK1 O3 QSPI1 output TXEN0A O4 ERAY0 output FCLP0 O5 MSC0 output ETHTXEN O6 ETH output COUT61 O7 CCU60 output P11.7 I TIN123 ETHRXD3 C9 GTM input LP / PU1 / VFLEX General-purpose input GTM input ETH input P11.7 O0 General-purpose output TOUT123 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P11.8 I TIN124 ETHRXD2 LP / PU1 / VFLEX General-purpose input GTM input ETH input P11.8 O0 General-purpose output TOUT124 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-152 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-31 Port 11 Functions (cont’d) Pin Symbol Ctrl Type Function B5 P11.9 I MP+ / PU1 / VFLEX General-purpose input TIN98 MTSR1B D5 GTM input QSPI1 input RXD0A1 ERAY0 input ETHRXD1 ETH input P11.9 O0 General-purpose output TOUT98 O1 GTM output – O2 Reserved MTSR1 O3 QSPI1 output – O4 Reserved SOP0 O5 MSC0 output – O6 Reserved COUT60 O7 CCU60 output P11.10 I TIN99 REQ12 LP / PU1 / VFLEX General-purpose input GTM input SCU input ARX1E ASCLIN1 input SLSI1A QSPI1 input RXDCAN3D CAN node 3 input RXD0B1 ERAY0 input ETHRXD0 ETH input SDI00 MSC0 input P11.10 O0 General-purpose output TOUT99 O1 GTM output – O2 Reserved SLSO03 O3 QSPI0 output SLSO13 O4 QSPI1 output – O5 Reserved – O6 Reserved CC62 O7 CCU60 output Data Sheet TOC-153 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-31 Port 11 Functions (cont’d) Pin Symbol Ctrl Type Function D6 P11.11 I MP+ / PU1 / VFLEX General-purpose input TIN100 ETHCRSDVA C5 GTM input ETH input ETHRXDVA ETH input ETHCRSB ETH input P11.11 O0 General-purpose output TOUT100 O1 GTM output END02 O2 MSC0 output SLSO04 O3 QSPI0 output SLSO14 O4 QSPI1 output EN00 O5 MSC0 output TXEN0B O6 ERAY0 output CC61 O7 CCU60 output P11.12 I TIN101 ETHREFCLK MPR / PU1 / VFLEX General-purpose input GTM input ETH input ETHTXCLKB ETH input (Not for productive purposes) ETHRXCLKA ETH input (Not for productive purposes) P11.12 O0 General-purpose output TOUT101 O1 GTM output ATX1 O2 ASCLIN1 output GTMCLK2 O3 GTM output TXD0B O4 ERAY0 output TXDCAN3 O5 CAN node 3 output EXTCLK1 O6 SCU output CC60 O7 CCU60 output Data Sheet TOC-154 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-31 Port 11 Functions (cont’d) Pin Symbol Ctrl Type Function B9 P11.13 I LP / PU1 / VFLEX General-purpose input TIN125 ETHRXERA SDA1A C8 ETH input I2C1 input P11.13 O0 General-purpose output TOUT125 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved SDA1 O6 I2C1 output – O7 Reserved P11.14 I TIN126 ETHCRSDVB C7 GTM input LP / PU1 / VFLEX General-purpose input GTM input ETH input ETHRXDVB ETH input ETHCRSA ETH input SCL1A I2C1 input P11.14 O0 General-purpose output TOUT126 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved SCL1 O6 I2C1 output – O7 Reserved P11.15 I TIN127 ETHCOL LP / PU1 / VFLEX General-purpose input GTM input ETH input P11.15 O0 General-purpose output TOUT127 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-155 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-32 Port 12 Functions Pin Symbol Ctrl Type Function A11 P12.0 I LP / PU1 / VFLEX General-purpose input TIN128 ETHRXCLKC RXDCAN0C GTM input ETH input CAN node 0 input P12.0 O0 General-purpose output TOUT128 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved ETHMDC O6 ETH output – O7 Reserved P12.1 B11 I TIN129 LP / PU1 / VFLEX General-purpose input GTM input P12.1 O0 General-purpose output TOUT129 O1 GTM output ASLSO3 O2 ASCLIN3 output – O3 Reserved – O4 Reserved TXDCAN0 O5 CAN node 0 output – O6 Reserved – O7 Reserved ETHMDIOC HWOU T ETH input/output Table 2-33 Port 13 Functions Pin Symbol Ctrl Type Function C17 P13.0 I LVDSM_N / PU1 / VEXT General-purpose input TIN91 GTM input P13.0 O0 TOUT91 O1 GTM output END03 O2 MSC0 output SCLK2N O3 QSPI2 output (LVDS) EN01 O4 MSC0 output FCLN0 O5 MSC0 output (LVDS) FCLND0 O6 MSC0 output (LVDS) – O7 Reserved Data Sheet TOC-156 General-purpose output V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-33 Port 13 Functions (cont’d) Pin Symbol Ctrl Type Function C18 P13.1 I LVDSM_P / PU1 / VEXT General-purpose input TIN92 SCL0B GTM input I2C0 input P13.1 O0 General-purpose output TOUT92 O1 GTM output – O2 Reserved SCLK2P O3 QSPI2 output (LVDS) – O4 Reserved FCLP0 O5 MSC0 output (LVDS) SCL0 O6 I2C0 output – O7 Reserved P13.2 D17 I TIN93 CAPINA LVDSM_N / PU1 / VEXT SDA0B General-purpose input GTM input GPT120 input I2C0 input P13.2 O0 General-purpose output TOUT93 O1 GTM output – O2 Reserved MTSR2N O3 QSPI2 output (LVDS) FCLP0 O4 MSC0 output SON0 O5 MSC0 output (LVDS) SDA0 O6 I2C0 output SOND0 O7 MSC0 output (LVDS) P13.3 C16 I TIN94 LVDSM_P / PU1 / VEXT General-purpose input GTM input P13.3 O0 TOUT94 O1 GTM output – O2 Reserved MTSR2P O3 QSPI2 output (LVDS) – O4 Reserved SOP0 O5 MSC0 output (LVDS) – O6 Reserved – O7 Reserved Data Sheet TOC-157 General-purpose output V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-33 Port 13 Functions (cont’d) Pin Symbol Ctrl Type Function B17 P13.4 I LVDSM_N / PU1 / VEXT General-purpose input TIN253 PSIRX4A GTM input PSI5 input P13.4 O0 General-purpose output TOUT253 O1 GTM output END22 O2 MSC2 output – O3 Reserved EN20 O4 MSC2 output FCLN2 O5 MSC2 output (LVDS) FCLND2 O6 MSC2 output (LVDS) – O7 Reserved P13.5 A17 I TIN254 LVDSM_P / PU1 / VEXT General-purpose input GTM input P13.5 O0 TOUT254 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved FCLP2 O5 MSC2 output (LVDS) – O6 Reserved – O7 Reserved P13.6 A16 I TIN255 LVDSM_N / PU1 / VEXT General-purpose output General-purpose input GTM input P13.6 O0 TOUT255 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved SON2 O5 MSC2 output (LVDS) SOND2 O6 MSC2 output (LVDS) – O7 Reserved Data Sheet TOC-158 General-purpose output V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-33 Port 13 Functions (cont’d) Pin Symbol Ctrl Type Function B16 P13.7 I LVDSM_P / PU1 / VEXT General-purpose input TIN256 GTM input P13.7 O0 TOUT256 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved SOP2 O5 MSC2 output (LVDS) – O6 Reserved – O7 Reserved P13.9 C12 I TIN248 SCL1B MP / PU1 / VEXT General-purpose output General-purpose input GTM input I2C1 input P13.9 O0 General-purpose output TOUT248 O1 GTM output ATX3 O2 ASCLIN3 output SLSO55 O3 QSPI5 output – O4 Reserved TXDCANr1 O5 CAN node 1 output (MultiCANr+) SCL1 O6 I2C1 output – O7 Reserved P13.10 A13 I TIN251 PSIRX3A LP / PU1 / VEXT General-purpose input GTM input PSI5 input P13.10 O0 General-purpose output TOUT251 O1 GTM output ATX0 O2 ASCLIN0 output – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-159 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-33 Port 13 Functions (cont’d) Pin Symbol Ctrl Type Function B13 P13.11 I LP / PU1 / VEXT General-purpose input TIN250 ARX0E GTM input ASCLIN0 input P13.11 O0 General-purpose output TOUT250 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved PSITX3 O5 PSI5 output – O6 Reserved – O7 Reserved P13.12 B12 I TIN249 ARX3H LP / PU1 / VEXT General-purpose input GTM input ASCLIN3 input RXDCANr1B CAN node 1 input (MultiCANr+) SDA1B I2C1 input P13.12 O0 General-purpose output TOUT249 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved SDA1 O6 I2C1 output – O7 Reserved P13.14 A12 I TIN252 LP / PU1 / VEXT General-purpose input GTM input P13.14 O0 TOUT252 O1 GTM output – O2 Reserved SLSO54 O3 QSPI5 output – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-160 General-purpose output V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-34 Port 14 Functions Pin Symbol Ctrl Type Function C21 P14.0 I MP+ / PU1 / VEXT General-purpose input TIN80 SENT12D GTM input SENT input P14.0 O0 General-purpose output TOUT80 O1 GTM output ATX0 O2 ASCLIN0 output Recommended as Boot loader pin TXD0A O3 ERAY0 output TXD0B O4 ERAY0 output TXDCAN1 O5 CAN node 1 output Used for single pin DAP (SPD) function ASCLK0 O6 ASCLIN0 output COUT62 O7 CCU60 output P14.1 D21 I TIN81 REQ15 MP / PU1 / VEXT General-purpose input GTM input SCU input SENT13D SENT input ARX0A ASCLIN0 input Recommended as Boot loader pin RXDCAN1B CAN node 1 input Used for single pin DAP (SPD) function RXD0A3 ERAY0 input RXD0B3 ERAY0 input EVRWUPA SCU input P14.1 O0 General-purpose output TOUT81 O1 GTM output ATX0 O2 ASCLIN0 output Recommended as Boot loader pin. – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved COUT63 O7 CCU60 output Data Sheet TOC-161 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-34 Port 14 Functions (cont’d) Pin Symbol Ctrl Type Function D20 P14.2 I LP / PU1 / VEXT General-purpose input TIN82 HWCFG2 EVR13 GTM input SCU input Latched at cold power on reset to decide EVR13 activation. P14.2 O0 General-purpose output TOUT82 O1 GTM output ATX2 O2 ASCLIN2 output SLSO21 O3 QSPI2 output – O4 Reserved – O5 Reserved ASCLK2 O6 ASCLIN2 output – O7 Reserved P14.3 C14 I TIN83 ARX2A LP / PU1 / VEXT General-purpose input GTM input ASCLIN2 input REQ10 SCU input HWCFG3_BMI SCU input SDI02 MSC0 input P14.3 O0 General-purpose output TOUT83 O1 GTM output ATX2 O2 ASCLIN2 output SLSO23 O3 QSPI2 output ASLSO1 O4 ASCLIN1 output ASLSO3 O5 ASCLIN3 output – O6 Reserved – O7 Reserved Data Sheet TOC-162 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-34 Port 14 Functions (cont’d) Pin Symbol Ctrl Type Function D13 P14.4 I LP / PU1 / VEXT General-purpose input TIN84 HWCFG6 GTM input SCU input Latched at cold power on reset to decide default pad reset state (PU or HighZ). P14.4 O0 General-purpose output TOUT84 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P14.5 C20 I TIN85 HWCFG1 EVR33 MP+ / PU1 / VEXT General-purpose input GTM input SCU input Latched at cold power on reset to decide EVR33 activation. P14.5 O0 General-purpose output TOUT85 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved TXD0B O6 ERAY0 output TXD1B O7 ERAY1 output P14.6 C13 I TIN86 HWCFG0 DCLDO MP+ / PU1 / VEXT General-purpose input GTM input SCU input If EVR13 active, latched at cold power on reset to decide between LDO and SMPS mode. P14.6 O0 General-purpose output TOUT86 O1 GTM output – O2 Reserved SLSO22 O3 QSPI2 output – O4 Reserved – O5 Reserved TXEN0B O6 ERAY0 output TXEN1B O7 ERAY1 output Data Sheet TOC-163 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-34 Port 14 Functions (cont’d) Pin Symbol Ctrl Type Function D12 P14.7 I LP / PU1 / VEXT General-purpose input TIN87 RXD0B0 RXD1B0 GTM input ERAY0 input ERAY1 input P14.7 O0 General-purpose output TOUT87 O1 GTM output ARTS0 O2 ASCLIN0 output SLSO24 O3 QSPI2 output – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P14.8 A14 I TIN88 ARX1D LP / PU1 / VEXT General-purpose input GTM input ASCLIN1 input RXDCAN2D CAN node 2 input RXD0A0 ERAY0 input RXD1A0 ERAY1 input P14.8 O0 General-purpose output TOUT88 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P14.9 C19 I TIN89 ACTS0A MP+ / PU1 / VEXT General-purpose input GTM input ASCLIN0 input P14.9 O0 General-purpose output TOUT89 O1 GTM output END03 O2 MSC0 output EN01 O3 MSC0 output – O4 Reserved TXEN0B O5 ERAY0 output TXEN0A O6 ERAY0 output TXEN1A O7 ERAY1 output Data Sheet TOC-164 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-34 Port 14 Functions (cont’d) Pin Symbol Ctrl Type Function C15 P14.10 I MP+ / PU1 / VEXT General-purpose input TIN90 GTM input P14.10 O0 TOUT90 O1 GTM output END02 O2 MSC0 output EN00 O3 MSC0 output ATX1 O4 ASCLIN1 output TXDCAN2 O5 CAN node 2 output TXD0A O6 ERAY0 output TXD1A O7 ERAY1 output P14.11 A19 I TIN258 LP / PU1 / VEXT General-purpose output General-purpose input GTM input P14.11 O0 TOUT258 O1 GTM output END20 O2 MSC2 output PSITX4 O3 PSI5 output EN22 O4 MSC2 output SOP2 O5 MSC2 output – O6 Reserved – O7 Reserved P14.12 A15 I TIN261 SDI20 LP / PU1 / VEXT General-purpose output General-purpose input GTM input MSC2 input P14.12 O0 General-purpose output TOUT261 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-165 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-34 Port 14 Functions (cont’d) Pin Symbol Ctrl Type Function B19 P14.13 I MP+ / PU1 / VEXT General-purpose input TIN260 GTM input P14.13 O0 TOUT260 O1 GTM output END23 O2 MSC2 output – O3 Reserved EN21 O4 MSC2 output – O5 Reserved – O6 Reserved – O7 Reserved P14.14 B15 I TIN259 MP+ / PU1 / VEXT General-purpose output General-purpose input GTM input P14.14 O0 TOUT259 O1 GTM output END22 O2 MSC2 output – O3 Reserved EN20 O4 MSC2 output – O5 Reserved – O6 Reserved – O7 Reserved P14.15 B14 I TIN263 INJ21 LP / PU1 / VEXT General-purpose output General-purpose input GTM input MSC2 output P14.15 O0 General-purpose output TOUT263 O1 GTM output ATX1 O2 ASCLIN1 output – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-166 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-35 Port 15 Functions Pin Symbol Ctrl Type Function C22 P15.1 I LP / PU1 / VEXT General-purpose input TIN72 REQ16 B21 GTM input SCU input ARX1A ASCLIN1 input RXDCAN2A CAN node 2 input SLSI2B QSPI2 input EVRWUPB SCU input P15.1 O0 General-purpose output TOUT72 O1 GTM output ATX1 O2 ASCLIN1 output SLSO25 O3 QSPI2 output – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P15.2 I TIN73 SLSI2A MP / PU1 / VEXT General-purpose input GTM input QSPI2 input MRST2E QSPI2 input SENT10D SENT input HSIC2INA QSPI2 input P15.2 O0 General-purpose output TOUT73 O1 GTM output ATX0 O2 ASCLIN0 output SLSO20 O3 QSPI2 output – O4 Reserved TXDCAN1 O5 CAN node 1 output ASCLK0 O6 ASCLIN0 output – O7 Reserved Data Sheet TOC-167 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-35 Port 15 Functions (cont’d) Pin Symbol Ctrl Type Function D18 P15.3 I MP / PU1 / VEXT General-purpose input TIN74 ARX0B A21 GTM input ASCLIN0 input SCLK2A QSPI2 input RXDCAN1A CAN node 1 input HSIC2INB QSPI2 input P15.3 O0 General-purpose output TOUT74 O1 GTM output ATX0 O2 ASCLIN0 output SCLK2 O3 QSPI2 output END03 O4 MSC0 output EN01 O5 MSC0 output – O6 Reserved – O7 Reserved P15.4 I TIN75 MRST2A MP / PU1 / VEXT General-purpose input GTM input QSPI2 input REQ0 SCU input SCL0C I2C0 input SENT11D SENT input P15.4 O0 General-purpose output TOUT75 O1 GTM output ATX1 O2 ASCLIN1 output MRST2 O3 QSPI2 output – O4 Reserved – O5 Reserved SCL0 O6 I2C0 output CC62 O7 CCU60 output Data Sheet TOC-168 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-35 Port 15 Functions (cont’d) Pin Symbol Ctrl Type Function D19 P15.5 I MP / PU1 / VEXT General-purpose input TIN76 ARX1B B20 ASCLIN1 input MTSR2A QSPI2 input REQ13 SCU input SDA0C I2C0 input P15.5 O0 General-purpose output TOUT76 O1 GTM output ATX1 O2 ASCLIN1 output MTSR2 O3 QSPI2 output END02 O4 MSC0 output EN00 O5 MSC0 output SDA0 O6 I2C0 output CC61 O7 CCU60 output P15.6 I TIN77 MTSR2B A20 GTM input MP / PU1 / VEXT General-purpose input GTM input QSPI2 input P15.6 O0 General-purpose output TOUT77 O1 GTM output ATX3 O2 ASCLIN3 output MTSR2 O3 QSPI2 output SLSO53 O4 QSPI5 output SCLK2 O5 QSPI2 output ASCLK3 O6 ASCLIN3 output CC60 O7 CCU60 output P15.7 I TIN78 ARX3A MRST2B MP / PU1 / VEXT General-purpose input GTM input ASCLIN3 input QSPI2 input P15.7 O0 General-purpose output TOUT78 O1 GTM output ATX3 O2 ASCLIN3 output MRST2 O3 QSPI2 output – O4 Reserved – O5 Reserved – O6 Reserved COUT60 O7 CCU60 output Data Sheet TOC-169 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-35 Port 15 Functions (cont’d) Pin Symbol Ctrl Type Function D16 P15.8 I MP / PU1 / VEXT General-purpose input TIN79 SCLK2B REQ1 GTM input QSPI2 input SCU input P15.8 O0 General-purpose output TOUT79 O1 GTM output – O2 Reserved SCLK2 O3 QSPI2 output – O4 Reserved – O5 Reserved ASCLK3 O6 ASCLIN3 output COUT61 O7 CCU60 output Table 2-36 Port 20 Functions Pin Symbol Ctrl Type Function A24 P20.0 I MP / PU1 / VEXT General-purpose input TIN59 RXDCAN3C GTM input CAN node 3 input RXDCANr1C CAN node 1 input (MultiCANr+) T6EUDA GPT120 input REQ9 SCU input SYSCLK HSCT input TGI0 OCDS input P20.0 O0 General-purpose output TOUT59 O1 GTM output ATX3 O2 ASCLIN3 output ASCLK3 O3 ASCLIN3 output – O4 Reserved SYSCLK O5 HSCT output – O6 Reserved – O7 Reserved TGO0 HWOU T OCDS; ENx Data Sheet TOC-170 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-36 Port 20 Functions (cont’d) Pin Symbol Ctrl Type Function B23 P20.2 I LP / PU1 / VEXT General-purpose input This pin is latched at power on reset release to enter test mode. TESTMODE OCDS input P20.2 O0 Output function not available – O1 Output function not available – O2 Output function not available – O3 Output function not available – O4 Output function not available – O5 Output function not available – O6 Output function not available – O7 Output function not available Table 2-37 Port 21 Functions Pin Symbol Ctrl Type Function J23 P21.0 I LVDSH_N/ PU1 / VDDP3 General-purpose input TIN51 MRST4DN HOLD GTM input QSPI4 input (LVDS) EBU input P21.0 O0 General-purpose output TOUT51 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved ETHMDC O6 ETH output BAABA0 O7 EBU output (combined for BAA and BA0) HSM1 O HSM output Data Sheet TOC-171 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-37 Port 21 Functions (cont’d) Pin Symbol Ctrl Type Function G24 P21.1 I LVDSH_P/ PU1 / VDDP3 General-purpose input TIN52 ETHMDIOB H23 GTM input ETH input (Not for production purposes) MRST4DP QSPI4 input (LVDS) WAIT EBU input P21.1 O0 General-purpose output TOUT52 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved ETHMDIO O6 ETH output (Not for production purposes) BREQBA1 O7 EBU output (combined for BREQ and BA1) HSM2 O HSM output P21.2 I TIN53 MRST2CN LVDSH_N/ PU1 / VDDP3 General-purpose input GTM input QSPI2 input (LVDS) MRST4CN QSPI4 input (LVDS) ARX3GN ASCLIN3 input (LVDS) EMGSTOPB SCU input RXDN HSCT input (LVDS) P21.2 O0 General-purpose output TOUT53 O1 GTM output ASLSO3 O2 ASCLIN3 output – O3 Reserved – O4 Reserved ETHMDC O5 ETH output SDRAMA8 O6 EBU output – O7 Reserved Data Sheet TOC-172 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-37 Port 21 Functions (cont’d) Pin Symbol Ctrl Type Function G23 P21.3 I LVDSH_P/ PU1 / VDDP3 General-purpose input TIN54 MRST2CP D26 QSPI2 input (LVDS) MRST4CP QSPI4 input (LVDS) ARX3GP ASCLIN3 input (LVDS) RXDP HSCT input (LVDS) P21.3 O0 General-purpose output TOUT54 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved SDRAMA9 O6 EBU output – O7 Reserved ETHMDIOD HWOUT ETH input/output P21.4 I TIN55 C26 GTM input LVDSH_N/ PU1 / VDDP3 General-purpose input GTM input P21.4 O0 TOUT55 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved SDRAMA10 O6 EBU output – O7 Reserved TXDN HSCT HSCT output (LVDS) P21.5 I TIN56 LVDSH_P/ PU1 / VDDP3 General-purpose output General-purpose input GTM input P21.5 O0 TOUT56 O1 GTM output ASCLK3 O2 ASCLIN3 output – O3 Reserved – O4 Reserved – O5 Reserved SDRAMA11 O6 EBU output – O7 Reserved TXDP HSCT HSCT output (LVDS) Data Sheet TOC-173 General-purpose output V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-37 Port 21 Functions (cont’d) Pin Symbol Ctrl Type Function E25 P21.6 I A2 / PU / VDDP3 General-purpose input TIN57 ARX3F D25 GTM input ASCLIN3 input TGI2 OCDS input TDI OCDS (JTAG) input T5EUDA GPT120 input P21.6 O0 General-purpose output TOUT57 O1 GTM output ASLSO3 O2 ASCLIN3 output – O3 Reserved – O4 Reserved SYSCLK O5 HSCT output SDRAMA12 O6 EBU output T3OUT O7 GPT120 output TGO2 HWOUT OCDS; ENx P21.7 I TIN58 DAP2 A2 / PU / VDDP3 General-purpose input GTM input OCDS (3-Pin DAP) input In the 3-Pin DAP mode this pin is used as DAP2. In the 2-PIN DAP mode this pin is used as P21.7 and controlled by the related port control logic TGI3 OCDS input ETHRXERB ETH input T5INA GPT120 input P21.7 O0 General-purpose output TOUT58 O1 GTM output ATX3 O2 ASCLIN3 output ASCLK3 O3 ASCLIN3 output – O4 Reserved – O5 Reserved SDRAMA13 O6 EBU output T6OUT O7 GPT120 output TGO3 HWOUT OCDS; ENx TDO OCDS (JTAG); ENx The JTAG TDO function is overlayed with P21.7 via a double bond. In JTAG mode this pin is used as TDO, after power-on reset it is HighZ. DAP2 OCDS (3-Pin DAP); ENx In the 3-Pin DAP mode this pin is used as DAP2. Data Sheet TOC-174 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-38 Port 22 Functions Pin Symbol Ctrl Type Function K23 P22.0 I LVDSM_N / PU1 / VEXT General-purpose input TIN47 MTSR4B J24 QSPI4 input P22.0 O0 General-purpose output TOUT47 O1 GTM output ATX3N O2 ASCLIN3 output (LVDS) MTSR4 O3 QSPI4 output SCLK4N O4 QSPI4 output (LVDS) FCLN1 O5 MSC1 output (LVDS) FCLND1 O6 MSC1 output (LVDS) – O7 Reserved P22.1 I TIN48 MRST4B J25 GTM input LVDSM_P / PU1 / VEXT General-purpose input GTM input QSPI4 input P22.1 O0 General-purpose output TOUT48 O1 GTM output ATX3P O2 ASCLIN3 output (LVDS) MRST4 O3 QSPI4 output SCLK4P O4 QSPI4 output (LVDS) FCLP1 O5 MSC1 output (LVDS) – O6 Reserved – O7 Reserved P22.2 I TIN49 SLSI4B LVDSM_N / PU1 / VEXT General-purpose input GTM input QSPI4 input P22.2 O0 General-purpose output TOUT49 O1 GTM output – O2 Reserved SLSO43 O3 QSPI4 output MTSR4N O4 QSPI4 output (LVDS) SON1 O5 MSC1 output (LVDS) SOND1 O6 MSC1 output (LVDS) – O7 Reserved Data Sheet TOC-175 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-38 Port 22 Functions (cont’d) Pin Symbol Ctrl Type Function J26 P22.3 I LVDSM_P / PU1 / VEXT General-purpose input TIN50 SCLK4B GTM input QSPI4 input P22.3 O0 General-purpose output TOUT50 O1 GTM output – O2 Reserved SCLK4 O3 QSPI4 output MTSR4P O4 QSPI4 output (LVDS) SOP1 O5 MSC1 output (LVDS) – O6 Reserved – O7 Reserved Table 2-39 Port 23 Functions Pin Symbol Ctrl Type Function M26 P23.0 I LP / PU1 / VEXT General-purpose input TIN41 L24 GTM input P23.0 O0 TOUT41 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P23.1 I TIN42 SDI10 MP+ / PU1 / VEXT General-purpose output General-purpose input GTM input MSC1 input P23.1 O0 General-purpose output TOUT42 O1 GTM output ARTS1 O2 ASCLIN1 output SLSO46 O3 QSPI4 output GTMCLK0 O4 GTM output – O5 Reserved EXTCLK0 O6 SCU output – O7 Reserved Data Sheet TOC-176 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-39 Port 23 Functions (cont’d) Pin Symbol Ctrl Type Function L25 P23.2 I LP / PU1 / VEXT General-purpose input TIN43 L26 P23.2 O0 TOUT43 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P23.3 I TIN44 INJ10 K24 GTM input LP / PU1 / VEXT General-purpose output General-purpose input GTM input MSC1 input P23.3 O0 General-purpose output TOUT44 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P23.4 I TIN45 MP+ / PU1 / VEXT General-purpose input GTM input P23.4 O0 TOUT45 O1 GTM output – O2 Reserved SLSO45 O3 QSPI4 output END12 O4 MSC1 output EN10 O5 MSC1 output – O6 Reserved – O7 Reserved Data Sheet General-purpose output TOC-177 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-39 Port 23 Functions (cont’d) Pin Symbol Ctrl Type Function K25 P23.5 I MP+ / PU1 / VEXT General-purpose input TIN46 K26 GTM input P23.5 O0 TOUT46 O1 GTM output – O2 Reserved SLSO44 O3 QSPI4 output END13 O4 MSC1 output EN11 O5 MSC1 output – O6 Reserved – O7 Reserved P23.6 I TIN138 LP / PU1 / VEXT General-purpose output General-purpose input GTM input P23.6 O0 General-purpose output TOUT138 O1 GTM output – O2 Reserved – O3 Reserved SLSO011 O4 QSPI0 output – O5 Reserved – O6 Reserved – O7 Reserved Table 2-40 Port 24 Functions Pin Symbol Ctrl Type Function U23 P24.0 I A2 / PU1 / VEBU General-purpose input TIN222 GTM input P24.0 O0 TOUT222 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ11 HWOU T EBU Data Bus Line (SDRAM) A11 Data Sheet General-purpose output EBU output TOC-178 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-40 Port 24 Functions (cont’d) Pin Symbol Ctrl Type Function T24 P24.1 I A2 / PU1 / VEBU General-purpose input TIN223 P24.1 O0 TOUT223 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ15 HWOU T EBU Data Bus Line (SDRAM) A15 T25 P24.2 I TIN224 General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P24.2 O0 TOUT224 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ14 HWOU T EBU Data Bus Line (SDRAM) A14 T26 GTM input P24.3 I TIN225 General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P24.3 O0 TOUT225 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ13 HWOU T EBU Data Bus Line (SDRAM) A13 Data Sheet General-purpose output EBU output TOC-179 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-40 Port 24 Functions (cont’d) Pin Symbol Ctrl Type Function R24 P24.4 I A2 / PU1 / VEBU General-purpose input TIN226 P24.4 O0 TOUT226 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ9 HWOU T EBU Data Bus Line (SDRAM) A9 R25 P24.5 I TIN227 General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P24.5 O0 TOUT227 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ12 HWOU T EBU Data Bus Line (SDRAM) A12 R26 GTM input P24.6 I TIN228 General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P24.6 O0 TOUT228 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ5 HWOU T EBU Data Bus Line (SDRAM) A5 Data Sheet General-purpose output EBU output TOC-180 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-40 Port 24 Functions (cont’d) Pin Symbol Ctrl Type Function P24 P24.7 I A2 / PU1 / VEBU General-purpose input TIN229 P24.7 O0 TOUT229 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ8 HWOU T EBU Data Bus Line (SDRAM) A8 P25 P24.8 I TIN230 General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P24.8 O0 TOUT230 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ10 HWOU T EBU Data Bus Line (SDRAM) A10 P26 GTM input P24.9 I TIN231 General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P24.9 O0 TOUT231 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ6 HWOU T EBU Data Bus Line (SDRAM) A6 Data Sheet General-purpose output EBU output TOC-181 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-40 Port 24 Functions (cont’d) Pin Symbol Ctrl Type Function N23 P24.10 I A2 / PU1 / VEBU General-purpose input TIN232 P24.10 O0 TOUT232 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ4 HWOU T EBU Data Bus Line (SDRAM) A4 N24 P24.11 I TIN233 General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P24.11 O0 TOUT233 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ3 HWOU T EBU Data Bus Line (SDRAM) A3 N25 GTM input P24.12 I TIN234 General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P24.12 O0 TOUT234 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ1 HWOU T EBU Data Bus Line (SDRAM) A1 Data Sheet General-purpose output EBU output TOC-182 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-40 Port 24 Functions (cont’d) Pin Symbol Ctrl Type Function N26 P24.13 I A2 / PU1 / VEBU General-purpose input TIN235 P24.13 O0 TOUT235 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ2 HWOU T EBU Data Bus Line (SDRAM) A2 M24 P24.14 I TIN236 General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P24.14 O0 TOUT236 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ0 HWOU T EBU Data Bus Line (SDRAM) A0 M25 GTM input P24.15 I TIN237 General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P24.15 O0 TOUT237 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved DQ7 HWOU T EBU Data Bus Line (SDRAM) A7 Data Sheet General-purpose output EBU output TOC-183 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-41 Port 25 Functions Pin Symbol Ctrl Type Function AA26 P25.0 I A2 / PU1 / VEBU General-purpose input TIN206 SDCLKI O0 General-purpose output TOUT206 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved BFCLKO HWOU T EBU output P25.1 I TIN207 EBU output A2 / PU1 / VEBU General-purpose input GTM input P25.1 O0 TOUT207 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved RD HWOU T EBU output RAS AA23 EBU input P25.0 SDCLKO AA24 GTM input P25.2 I TIN208 General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P25.2 O0 TOUT208 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved RD/WR HWOU T EBU output WR Data Sheet General-purpose output EBU output TOC-184 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-41 Port 25 Functions (cont’d) Pin Symbol Ctrl Type Function Y24 P25.3 I A2 / PU1 / VEBU General-purpose input TIN209 HOLDA O0 General-purpose output TOUT209 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved BAABA0 O7 EBU output (combined for BAA and BA0) CS2 HWOU T EBU output EBU output HOLDA P25.4 EBU output I TIN210 A2 / PU1 / VEBU General-purpose input GTM input P25.4 O0 TOUT210 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved CS1 HWOU T EBU output DQM0 Y26 EBU input P25.3 DQM1 Y25 GTM input P25.5 I TIN211 General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P25.5 O0 TOUT211 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved CS0 HWOU T EBU output Data Sheet General-purpose output TOC-185 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-41 Port 25 Functions (cont’d) Pin Symbol Ctrl Type Function W24 P25.7 I A2 / PU1 / VEBU General-purpose input TIN213 P25.7 O0 TOUT213 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved ADV HWOU T EBU output CAS W25 P25.8 I TIN214 W26 GTM input General-purpose output EBU output A2 / PU1 / VEBU General-purpose input GTM input P25.8 O0 TOUT214 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved A23 O5 EBU output SDRAMA0 O6 EBU output – O7 Reserved BC0 HWOU T EBU output P25.9 I TIN215 A2 / PU1 / VEBU General-purpose output General-purpose input GTM input P25.9 O0 TOUT215 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved A22 O5 EBU output SDRAMA1 O6 EBU output – O7 Reserved BC1 HWOU T EBU output Data Sheet General-purpose output TOC-186 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-41 Port 25 Functions (cont’d) Pin Symbol Ctrl Type Function V24 P25.10 I A2 / PU1 / VEBU General-purpose input TIN216 V25 P25.10 O0 TOUT216 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved A21 O5 EBU output SDRAMA2 O6 EBU output – O7 Reserved BC2 HWOU T EBU output P25.11 I TIN217 V26 GTM input A2 / PU1 / VEBU General-purpose output General-purpose input GTM input P25.11 O0 TOUT217 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved A20 O5 EBU output SDRAMA3 O6 EBU output – O7 Reserved BC3 HWOU T EBU output P25.12 I TIN218 A2 / PU1 / VEBU General-purpose output General-purpose input GTM input P25.12 O0 TOUT218 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved SDRAMA4 O6 EBU output – O7 Reserved A19 HWOU T EBU output Data Sheet General-purpose output TOC-187 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-41 Port 25 Functions (cont’d) Pin Symbol Ctrl Type Function U24 P25.13 I A2 / PU1 / VEBU General-purpose input TIN219 U25 P25.13 O0 TOUT219 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved SDRAMA5 O6 EBU output – O7 Reserved A17 HWOU T EBU output P25.14 I TIN220 U26 GTM input A2 / PU1 / VEBU General-purpose output General-purpose input GTM input P25.14 O0 TOUT220 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved SDRAMA6 O6 EBU output – O7 Reserved A18 HWOU T EBU output P25.15 I TIN221 A2 / PU1 / VEBU General-purpose output General-purpose input GTM input P25.15 O0 TOUT221 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved SDRAMA7 O6 EBU output – O7 Reserved A16 HWOU T EBU output Data Sheet General-purpose output TOC-188 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-42 Port 26 Functions Pin Symbol Ctrl Type Function AA25 P26.0 I LP / PU1 / VFLEXE General-purpose input TIN212 BFCLKI GTM input EBU input P26.0 O0 General-purpose output TOUT212 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Table 2-43 Port 30 Functions Pin Symbol Ctrl Type Function AF22 P30.0 I MP / PU1 / VFLEXE General-purpose input TIN190 AF23 GTM input P30.0 O0 TOUT190 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD14 HWOU T EBU Address / Data Bus Line P30.1 I TIN191 MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P30.1 O0 TOUT191 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD11 HWOU T EBU Address / Data Bus Line Data Sheet General-purpose output TOC-189 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-43 Port 30 Functions (cont’d) Pin Symbol Ctrl Type Function AB24 P30.2 I MP / PU1 / VFLEXE General-purpose input TIN192 AC24 P30.2 O0 TOUT192 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD12 HWOU T EBU Address / Data Bus Line P30.3 I TIN193 AD24 GTM input MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P30.3 O0 TOUT193 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD15 HWOU T EBU Address / Data Bus Line P30.4 I TIN194 MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P30.4 O0 TOUT194 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD8 HWOU T EBU Address / Data Bus Line Data Sheet General-purpose output TOC-190 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-43 Port 30 Functions (cont’d) Pin Symbol Ctrl Type Function AE24 P30.5 I MP / PU1 / VFLEXE General-purpose input TIN195 AF24 P30.5 O0 TOUT195 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD13 HWOU T EBU Address / Data Bus Line P30.6 I TIN196 AB25 GTM input MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P30.6 O0 TOUT196 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD4 HWOU T EBU Address / Data Bus Line P30.7 I TIN197 MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P30.7 O0 TOUT197 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD7 HWOU T EBU Address / Data Bus Line Data Sheet General-purpose output TOC-191 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-43 Port 30 Functions (cont’d) Pin Symbol Ctrl Type Function AC25 P30.8 I MP / PU1 / VFLEXE General-purpose input TIN198 AD25 P30.8 O0 TOUT198 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD3 HWOU T EBU Address / Data Bus Line P30.9 I TIN199 AE25 GTM input MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P30.9 O0 TOUT199 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD0 HWOU T EBU Address / Data Bus Line P30.10 I TIN200 MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P30.10 O0 TOUT200 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD5 HWOU T EBU Address / Data Bus Line Data Sheet General-purpose output TOC-192 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-43 Port 30 Functions (cont’d) Pin Symbol Ctrl Type Function AF25 P30.11 I MP / PU1 / VFLEXE General-purpose input TIN201 AB26 P30.11 O0 TOUT201 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD10 HWOU T EBU Address / Data Bus Line P30.12 I TIN202 AC26 GTM input MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P30.12 O0 TOUT202 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD9 HWOU T EBU Address / Data Bus Line P30.13 I TIN203 MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P30.13 O0 TOUT203 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD2 HWOU T EBU Address / Data Bus Line Data Sheet General-purpose output TOC-193 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-43 Port 30 Functions (cont’d) Pin Symbol Ctrl Type Function AD26 P30.14 I MP / PU1 / VFLEXE General-purpose input TIN204 AE26 GTM input P30.14 O0 TOUT204 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD1 HWOU T EBU Address / Data Bus Line P30.15 I TIN205 MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P30.15 O0 General-purpose output TOUT205 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD6 HWOU T EBU Address / Data Bus Line Table 2-44 Port 31 Functions Pin Symbol Ctrl Type Function AD18 P31.0 I MP / PU1 / VFLEXE General-purpose input TIN174 GTM input P31.0 O0 TOUT174 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD30 HWOU T EBU Address / Data Bus Line Data Sheet General-purpose output TOC-194 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-44 Port 31 Functions (cont’d) Pin Symbol Ctrl Type Function AE18 P31.1 I MP / PU1 / VFLEXE General-purpose input TIN175 AF18 P31.1 O0 TOUT175 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD29 HWOU T EBU Address / Data Bus Line P31.2 I TIN176 AD19 GTM input MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P31.2 O0 TOUT176 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD28 HWOU T EBU Address / Data Bus Line P31.3 I TIN177 MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P31.3 O0 TOUT177 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD26 HWOU T EBU Address / Data Bus Line Data Sheet General-purpose output TOC-195 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-44 Port 31 Functions (cont’d) Pin Symbol Ctrl Type Function AE19 P31.4 I MP / PU1 / VFLEXE General-purpose input TIN178 AF19 P31.4 O0 TOUT178 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD24 HWOU T EBU Address / Data Bus Line P31.5 I TIN179 AD20 GTM input MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P31.5 O0 TOUT179 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD23 HWOU T EBU Address / Data Bus Line P31.6 I TIN180 MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P31.6 O0 TOUT180 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD20 HWOU T EBU Address / Data Bus Line Data Sheet General-purpose output TOC-196 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-44 Port 31 Functions (cont’d) Pin Symbol Ctrl Type Function AE20 P31.7 I MP / PU1 / VFLEXE General-purpose input TIN181 AF20 P31.7 O0 TOUT181 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD16 HWOU T EBU Address / Data Bus Line P31.8 I TIN182 AD21 GTM input MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P31.8 O0 TOUT182 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD31 HWOU T EBU Address / Data Bus Line P31.9 I TIN183 MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P31.9 O0 TOUT183 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD27 HWOU T EBU Address / Data Bus Line Data Sheet General-purpose output TOC-197 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-44 Port 31 Functions (cont’d) Pin Symbol Ctrl Type Function AE21 P31.10 I MP / PU1 / VFLEXE General-purpose input TIN184 AF21 P31.10 O0 TOUT184 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD21 HWOU T EBU Address / Data Bus Line P31.11 I TIN185 AD22 GTM input MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P31.11 O0 TOUT185 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD25 HWOU T EBU Address / Data Bus Line P31.12 I TIN186 MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P31.12 O0 TOUT186 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD19 HWOU T EBU Address / Data Bus Line Data Sheet General-purpose output TOC-198 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-44 Port 31 Functions (cont’d) Pin Symbol Ctrl Type Function AE22 P31.13 I MP / PU1 / VFLEXE General-purpose input TIN187 AD23 P31.13 O0 TOUT187 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD22 HWOU T EBU Address / Data Bus Line P31.14 I TIN188 AE23 GTM input MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P31.14 O0 TOUT188 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD18 HWOU T EBU Address / Data Bus Line P31.15 I TIN189 MP / PU1 / VFLEXE General-purpose output General-purpose input GTM input P31.15 O0 TOUT189 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved AD17 HWOU T EBU Address / Data Bus Line Data Sheet General-purpose output TOC-199 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-45 Port 32 Functions Pin Symbol Ctrl Type Function AD17 P32.0 I LP / PX/ VEXT General-purpose input TIN36 FDEST VGATE1N GTM input PMU input SMPS mode: analog output. External Pass Device gate control for EVR13 P32.0 O0 General-purpose output TOUT36 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P32.2 AE13 I TIN38 ARX3D LP / PU1 / VEXT General-purpose input GTM input ASCLIN3 input RXDCAN3B CAN node 3 input RXDCANr1D CAN node 1 input (MultiCANr+) P32.2 O0 General-purpose output TOUT38 O1 GTM output ATX3 O2 ASCLIN3 output – O3 Reserved – O4 Reserved – O5 Reserved DCDCSYNC O6 SCU output – O7 Reserved P32.3 AF13 I TIN39 LP / PU1 / VEXT General-purpose input GTM input P32.3 O0 TOUT39 O1 GTM output ATX3 O2 ASCLIN3 output – O3 Reserved ASCLK3 O4 ASCLIN3 output TXDCAN3 O5 CAN node 3 output TXDCANr1 O6 CAN node 1 output (MultiCANr+) – O7 Reserved Data Sheet General-purpose output TOC-200 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-45 Port 32 Functions (cont’d) Pin Symbol Ctrl Type Function AC14 P32.4 I MP+ / PU1 / VEXT General-purpose input TIN40 ACTS1B SDI12 GTM input ASCLIN1 input MSC1 input P32.4 O0 General-purpose output TOUT40 O1 GTM output – O2 Reserved END12 O3 MSC1 output GTMCLK1 O4 GTM output EN10 O5 MSC1 output EXTCLK1 O6 SCU output COUT63 O7 CCU60 output P32.5 AD14 I TIN140 LP / PU1 / VEXT General-purpose input GTM input P32.5 O0 TOUT140 O1 GTM output ATX2 O2 ASCLIN2 output – O3 Reserved – O4 Reserved – O5 Reserved TXDCAN2 O6 CAN node 2 output – O7 Reserved P32.6 AE17 I TGI4 TIN141 LP / PU1 / VEXT General-purpose output General-purpose input OCDS input GTM input RXDCAN2C CAN node 2 input ARX2F ASCLIN2 input P32.6 O0 General-purpose output TOUT141 O1 GTM output – O2 Reserved – O3 Reserved SLSO212 O4 QSPI2 output – O5 Reserved – O6 Reserved – O7 Reserved TGO4 HWOU T OCDS; ENx Data Sheet TOC-201 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-45 Port 32 Functions (cont’d) Pin Symbol Ctrl Type Function AF17 P32.7 I LP / PU1 / VEXT General-purpose input TIN142 TGI5 GTM input OCDS input P32.7 O0 General-purpose output TOUT142 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved TGO5 HWOU T OCDS; ENx Table 2-46 Port 33 Functions Pin Symbol Ctrl Type Function AC11 P33.0 I LP / PU1 / VEXT General-purpose input TIN22 DSITR0E GTM input DSADC channel 0 input E P33.0 O0 General-purpose output TOUT22 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved VADCG2BFL0 O6 VADC output – O7 Reserved Data Sheet TOC-202 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-46 Port 33 Functions (cont’d) Pin Symbol Ctrl Type Function AD11 P33.1 I LP / PU1 / VEXT General-purpose input TIN23 PSIRX0C GTM input PSI5 input SENT9C SENT input DSCIN2B DSADC channel 2 input B DSITR1E DSADC channel 1 input E P33.1 O0 General-purpose output TOUT23 O1 GTM output ASLSO3 O2 ASCLIN3 output SCLK2 O3 QSPI2 output DSCOUT2 O4 DSADC channel 2 output VADCEMUX02 O5 VADC output VADCG2BFL1 O6 VADC output – O7 Reserved P33.2 AE11 I TIN24 SENT8C LP / PU1 / VEXT General-purpose input GTM input SENT input DSDIN2B DSADC channel 2 input B DSITR2E DSADC channel 2 input E P33.2 O0 General-purpose output TOUT24 O1 GTM output ASCLK3 O2 ASCLIN3 output SLSO210 O3 QSPI2 output PSITX0 O4 PSI5 output VADCEMUX01 O5 VADC output VADCG2BFL2 O6 VADC output – O7 Reserved Data Sheet TOC-203 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-46 Port 33 Functions (cont’d) Pin Symbol Ctrl Type Function AF11 P33.3 I LP / PU1 / VEXT General-purpose input TIN25 PSIRX1C GTM input PSI5 input SENT7C SENT input DSCIN1B DSADC channel 1 input B P33.3 O0 General-purpose output TOUT25 O1 GTM output – O2 Reserved – O3 Reserved DSCOUT1 O4 DSADC channel 1 output VADCEMUX00 O5 VADC output VADCG2BFL3 O6 VADC output – O7 Reserved P33.4 AC12 I TIN26 SENT6C LP / PU1 / VEXT General-purpose input GTM input SENT input CTRAPC CCU61 input DSDIN1B DSADC channel 1 input DSITR0F DSADC channel 0 input F P33.4 O0 General-purpose output TOUT26 O1 GTM output ARTS2 O2 ASCLIN2 output SLSO212 O3 QSPI2 output PSITX1 O4 PSI5 output VADCEMUX12 O5 VADC output VADCG0BFL0 O6 VADC output – O7 Reserved Data Sheet TOC-204 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-46 Port 33 Functions (cont’d) Pin Symbol Ctrl Type Function AD12 P33.5 I LP / PU1 / VEXT General-purpose input TIN27 ACTS2B GTM input ASCLIN2 input PSIRX2C PSI5 input PSISRXC PSI5-S input SENT5C SENT input CCPOS2C CCU61 input T4EUDB GPT120 input DSCIN0B DSADC channel 0 input B DSITR1F DSADC channel 1 input F P33.5 O0 General-purpose output TOUT27 O1 GTM output SLSO07 O2 QSPI0 output SLSO17 O3 QSPI1 output DSCOUT0 O4 DSADC channel 0 output VADCEMUX11 O5 VADC output VADCG0BFL1 O6 VADC output – O7 Reserved P33.6 AE12 I TIN28 SENT4C LP / PU1 / VEXT General-purpose input GTM input SENT input CCPOS1C CCU61 input T2EUDB GPT120 input DSDIN0B DSADC channel 0 input B DSITR2F DSADC channel 2 input F P33.6 O0 General-purpose output TOUT28 O1 GTM output ASLSO2 O2 ASCLIN2 output SLSO211 O3 QSPI2 output PSITX2 O4 PSI5 output VADCEMUX10 O5 VADC output VADCG1BFL0 O6 VADC output PSISTX O7 PSI5-S output Data Sheet TOC-205 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-46 Port 33 Functions (cont’d) Pin Symbol Ctrl Type Function AC15 P33.7 I LP / PU1 / VEXT General-purpose input TIN29 RXDCAN0E GTM input CAN node 0 input REQ8 SCU input CCPOS0C CCU61 input T2INB GPT120 input P33.7 O0 General-purpose output TOUT29 O1 GTM output ASCLK2 O2 ASCLIN2 output SLSO47 O3 QSPI4 output – O4 Reserved – O5 Reserved VADCG1BFL1 O6 VADC output – O7 Reserved P33.8 AD15 I TIN30 ARX2E MP / HighZ / VEXT EMGSTOPA General-purpose input GTM input ASCLIN2 input SCU input P33.8 O0 General-purpose output TOUT30 O1 GTM output ATX2 O2 ASCLIN2 output SLSO42 O3 QSPI4 output – O4 Reserved TXDCAN0 O5 CAN node 0 output – O6 Reserved COUT62 O7 CCU61 output SMUFSP HWOU T SMU P33.9 AF12 I TIN31 HSIC3INA LP / PU1 / VEXT General-purpose input GTM input QSPI3 input P33.9 O0 General-purpose output TOUT31 O1 GTM output ATX2 O2 ASCLIN2 output SLSO41 O3 QSPI4 output ASCLK2 O4 ASCLIN2 output – O5 Reserved – O6 Reserved CC62 O7 CCU61 output Data Sheet TOC-206 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-46 Port 33 Functions (cont’d) Pin Symbol Ctrl Type Function AE14 P33.10 I MP / PU1 / VEXT General-purpose input TIN32 SLSI4A HSIC3INB GTM input QSPI4 input QSPI3 input P33.10 O0 General-purpose output TOUT32 O1 GTM output SLSO16 O2 QSPI1 output SLSO40 O3 QSPI4 output ASLSO1 O4 ASCLIN1 output PSISCLK O5 PSI5-S output – O6 Reserved COUT61 O7 CCU61 output P33.11 AF14 I TIN33 SCLK4A MP / PU1 / VEXT General-purpose input GTM input QSPI4 input P33.11 O0 General-purpose output TOUT33 O1 GTM output ASCLK1 O2 ASCLIN1 output SCLK4 O3 QSPI4 output – O4 Reserved – O5 Reserved DSCGPWMN O6 DSADC channel output CC61 O7 CCU61 output P33.12 AF15 I TIN34 MTSR4A MP / PU1 / VEXT General-purpose input GTM input QSPI4 input P33.12 O0 General-purpose output TOUT34 O1 GTM output ATX1 O2 ASCLIN1 output MTSR4 O3 QSPI4 output ASCLK1 O4 ASCLIN1 output – O5 Reserved DSCGPWMP O6 DSADC output COUT60 O7 CCU61 output Data Sheet TOC-207 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-46 Port 33 Functions (cont’d) Pin Symbol Ctrl Type Function AE15 P33.13 I MP / PU1 / VEXT General-purpose input TIN35 ARX1F GTM input ASCLIN1 input MRST4A QSPI4 input DSSGNB DSADC channel input B INJ11 MSC1 input P33.13 O0 General-purpose output TOUT35 O1 GTM output ATX1 O2 ASCLIN1 output MRST4 O3 QSPI4 output SLSO26 O4 QSPI2 output – O5 Reserved DCDCSYNC O6 SCU output CC60 O7 CCU61 output P33.14 AC13 I TIN143 TGI6 SCLK2D LP / PU1 / VEXT General-purpose input GTM input OCDS input QSPI2 input P33.14 O0 General-purpose output TOUT143 O1 GTM output – O2 Reserved SCLK2 O3 QSPI2 output – O4 Reserved – O5 Reserved – O6 Reserved CC62 O7 CCU60 output TGO6 HWOU T OCDS; ENx Data Sheet TOC-208 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-46 Port 33 Functions (cont’d) Pin Symbol Ctrl Type Function AD13 P33.15 I LP / PU1 / VEXT General-purpose input TIN144 TGI7 GTM input OCDS input P33.15 O0 General-purpose output TOUT144 O1 GTM output – O2 Reserved SLSO211 O3 QSPI2 output – O4 Reserved – O5 Reserved – O6 Reserved COUT62 O7 CCU60 output TGO7 HWOU T OCDS; ENx Table 2-47 Port 34 Functions Pin Symbol Ctrl Type Function AC9 P34.1 I LP / PU1 / VEXT General-purpose input TIN146 AC10 GTM input P34.1 O0 TOUT146 O1 GTM output ATX0 O2 ASCLIN0 output – O3 Reserved TXDCAN0 O4 CAN node 0 output TXDCANr0 O5 CAN node 0 output (MultiCANr+) – O6 Reserved COUT63 O7 CCU60 output P34.2 I TIN147 ARX0D LP / PU1 / VEXT General-purpose output General-purpose input GTM input ASCLIN0 input RXDCAN0G CAN node 0 input RXDCANr0C CAN node 0 input (MultiCANr+) P34.2 O0 General-purpose output TOUT147 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved CC60 O7 CCU60 output Data Sheet TOC-209 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-47 Port 34 Functions (cont’d) Pin Symbol Ctrl Type Function AF10 P34.3 I LP / PU1 / VEXT General-purpose input TIN148 AD10 P34.3 O0 TOUT148 O1 GTM output – O2 Reserved – O3 Reserved SLSO210 O4 QSPI2 output – O5 Reserved – O6 Reserved COUT60 O7 CCU60 output P34.4 I TIN149 MRST2D AE10 GTM input LP / PU1 / VEXT General-purpose output General-purpose input GTM input QSPI2 input P34.4 O0 General-purpose output TOUT149 O1 GTM output – O2 Reserved – O3 Reserved MRST2 O4 QSPI2 output – O5 Reserved – O6 Reserved CC61 O7 CCU60 output P34.5 I TIN150 MTSR2D LP / PU1 / VEXT General-purpose input GTM input QSPI2 input P34.5 O0 General-purpose output TOUT150 O1 GTM output – O2 Reserved – O3 Reserved MTSR2 O4 QSPI2 output – O5 Reserved – O6 Reserved COUT61 O7 CCU60 output Data Sheet TOC-210 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-48 Port 40 Functions Pin Symbol Ctrl Type Function AC7 P40.0 I S/ HighZ / VDDM General-purpose input VADCG3.0 DS2PB VADC analog input channel 0 of group 3 DSADC: positive analog input of channel 2, pin B CCPOS0D CCU60 input SENT0A SENT input P40.1 AD7 I VADCG3.1 S/ HighZ / VDDM General-purpose inpu.t VADC analog input channel 1 of group 3 (with pull down diagnostics) DS2NB DSADC: negative analog input channel 2, pin B CCPOS1B CCU60 input SENT1A SENT input P40.2 AA2 I VADCG3.2 S/ HighZ / VDDM General-purpose inpu.t VADC analog input channel 2 of group 3 (with pull down diagnostics) CCPOS1D CCU60 input SENT2A SENT input P40.3 AB2 I VADCG3.3 S/ HighZ / VDDM General-purpose input VADC analog input channel 3 of group 3 (with pull down diagnostics) CCPOS2B CCU60 input SENT3A SENT input P40.4 W3 I VADCG4.0 CCPOS2D S/ HighZ / VDDM SENT4A P40.5 Y3 I CCPOS0D S/ HighZ / VDDM SENT5A P40.6 VADCG4.4 DS3PA VADC analog input channel 0 of group 4 CCU60 input SENT input VADCG4.1 V4 General-purpose input General-purpose input VADC analog input channel 1 of group 4 CCU61 input SENT input I S/ HighZ / VDDM General-purpose input VADC analog input channel 4 of group 4 DSADC: positive analog input of channel 3, pin A CCPOS1B CCU61 input SENT6A SENT input Data Sheet TOC-211 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-48 Port 40 Functions (cont’d) Pin Symbol Ctrl Type Function V3 P40.7 I S/ HighZ / VDDM General-purpose input VADCG4.5 DS3NA VADC analog input channel 5 of group 4 DSADC: negative analog input channel 3, pin A CCPOS1D CCU61 input SENT7A SENT input P40.11 V2 I VADCG10.4 DS8PA S/ HighZ / VDDM SENT11A P40.12 W1 I DS8NA S/ HighZ / VDDM SENT12A P40.13 I DS9PA S/ HighZ / VDDM SENT13A P40.14 DSADC: positive analog input of channel 8, pin A General-purpose input VADC analog input channel 5 of group 10 DSADC: positive analog input of channel 8, pin A SENT input VADCG10.6 V1 VADC analog input channel 4 of group 10 SENT input VADCG10.5 U2 General-purpose input General-purpose input VADC analog input channel 6 of group 10 DSADC: positive analog input of channel 9, pin A SENT input I VADCG10.7 DS9NA S/ HighZ / VDDM SENT14A General-purpose input VADC analog input channel 7 of group 10 DSADC: positive analog input of channel 9, pin A SENT input Table 2-49 Analog Inputs Pin Symbol Ctrl Type AC5 AN0 I D / HighZ / Analog input 0 VDDM VADC analog input channel 0 of group 0 VADCG0.0 DS1PA AN1 AD5 DSADC: positive analog input of channel 1, pin A I VADCG0.1 DS1NA AN2 AE4 I DS0PA AN3 I DS0NA AN4 VADCG0.4 Data Sheet D / HighZ / Analog input 2 VDDM VADC analog input channel 2 of group 0 DSADC: positive analog input of channel 0, pin A VADCG0.3 AC2 D / HighZ / Analog input 1 VDDM VADC analog input channel 1 of group 0 DSADC: negative analog input channel 1, pin A VADCG0.2 AF4 Function D / HighZ / Analog input 3 VDDM VADC analog input channel 3 of group 0 DSADC: negative analog input channel 0, pin A I D / HighZ / Analog input 4 VDDM VADC analog input channel 4 of group 0 TOC-212 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-49 Analog Inputs (cont’d) Pin Symbol Ctrl Type AA3 AN5 I D / HighZ / Analog input 5 VDDM VADC analog input channel 5 of group 0 I D / HighZ / Analog input 6 VDDM VADC analog input channel 6 of group 0 I D / HighZ / Analog input 7 VDDM VADC analog input channel 7 of group 0 I D / HighZ / Analog input 8 VDDM VADC analog input channel 0 of group 1 I D / HighZ / Analog input 9 VDDM VADC analog input channel 1 of group 1 I D / HighZ / Analog input 10 VDDM VADC analog input channel 2 of group 1 I D / HighZ / Analog input 11 VDDM VADC analog input channel 3 of group 1 (with pull down diagnostics) I D / HighZ / Analog input 16 VDDM VADC analog input channel 0 of group 2 I D / HighZ / Analog input 17 VDDM VADC analog input channel 1 of group 2 I D / HighZ / Analog input 18 VDDM VADC analog input channel 2 of group 2 I D / HighZ / Analog input 19 VDDM VADC analog input channel 3 of group 2 (with pull down diagnostics) I D / HighZ / Analog input 20 VDDM VADC analog input channel 4 of group 2 VADCG0.5 AN6 AD1 VADCG0.6 AN7 AB4 VADCG0.7 AN8 AC4 VADCG1.0 AN9 AD4 VADCG1.1 AN10 AE3 VADCG1.2 AN11 AF3 VADCG1.3 AN16 AC3 VADCG2.0 AN17 AD3 VADCG2.1 AN18 AE2 VADCG2.2 AN19 AF2 VADCG2.3 AN20 AC8 VADCG2.4 Function DS2PA AN21 AD8 DSADC: positive analog input of channel 2, pin A I VADCG2.5 D / HighZ / Analog input 21 VDDM VADC analog input channel 5 of group 2 DS2NA AN22 AE8 DSADC: negative analog input channel 2, pin A I D / HighZ / Analog input 22 VDDM VADC analog input channel 6 of group 2 I D / HighZ / Analog input 23 VDDM VADC analog input channel 7 of group 2 I S/ HighZ / VDDM VADCG2.6 AN23 AF8 VADCG2.7 AN24 AC7 VADCG3.0 DS2PB SENT0A Data Sheet Analog input 24 VADC analog input channel 0 of group 3 DSADC: positive analog input of channel 2, pin B SENT input channel 0, pin A TOC-213 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-49 Analog Inputs (cont’d) Pin Symbol Ctrl Type Function AD7 AN25 I S/ HighZ / VDDM Analog input 24 VADCG3.1 VADC analog input channel 1 of group 3 (with pull down diagnostics) DS2NB DSADC: negative analog input channel 2, pin B SENT1A SENT input channel 1, pin A AN26 AA2 I VADCG3.2 S/ HighZ / VDDM SENT2A AN27 AB2 I S/ HighZ / VDDM SENT3A AN28 AN29 AN32 D / HighZ / Analog input 28 VDDM VADC analog input channel 4 of group 3 (with pull down diagnostics) I D / HighZ / Analog input 29 VDDM VADC analog input channel 5 of group 3 (with pull down diagnostics) I S/ HighZ / VDDM VADCG4.0 SENT4A AN33 Y3 I VADCG4.1 SENT5A AN36 V4 I VADCG4.4 DS3PA S/ HighZ / VDDM S/ HighZ / VDDM SENT6A AN37 V3 I DS3NA SENT7A AN40 AN41 AN42 VADCG5.2 Data Sheet SENT input channel 4, pin A Analog input 33 VADC analog input channel 1 of group 4 SENT input channel 5, pin A Analog input 34 VADC analog input channel 4 of group 4 DSADC: positive analog input of channel 3, pin A S/ HighZ / VDDM Analog input 37 VADC analog input channel 5 of group 4 DSADC: negative analog input channel 3, pin A I D / HighZ / Analog input 40 VDDM VADC analog input channel 0 of group 5 I D / HighZ / Analog input 41 VDDM VADC analog input channel 1 of group 5 I D / HighZ / Analog input 42 VDDM VADC analog input channel 2 of group 5 VADCG5.1 T1 VADC analog input channel 0 of group 4 SENT input channel 7, pin A VADCG5.0 U3 Analog input 32 SENT input channel 6, pin A VADCG4.5 U4 VADC analog input channel 3 of group 3 (with pull down diagnostics) I VADCG3.5 W3 Analog input 27 SENT input channel 3, pin A VADCG3.4 AC1 VADC analog input channel 2 of group 3 (with pull down diagnostics) SENT input channel 2, pin A VADCG3.3 AB1 Analog input 26 TOC-214 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-49 Analog Inputs (cont’d) Pin Symbol Ctrl Type U1 AN43 I D / HighZ / Analog input 43 VDDM VADC analog input channel 3 of group 5 (with pull down diagnostics) I D / HighZ / Analog input 48 VDDM VADC analog input channel 0 of group 8 I D / HighZ / Analog input 49 VDDM VADC analog input channel 1 of group 8 (muxtest) I D / HighZ / Analog input 52 VDDM VADC analog input channel 4 of group 8 VADCG5.3 AN48 AD2 VADCG8.0 AN49 AE1 VADCG8.1 AN52 AE6 VADCG8.4 Function DS6PA AN53 AF6 DSADC: positive analog input of channel 6, pin A I VADCG8.5 D / HighZ / Analog input 53 VDDM VADC analog input channel 5 of group 8 DS6NA AN54 AE7 DSADC: negative analog input channel 6, pin A I VADCG8.6 D / HighZ / Analog input 5 VDDM VADC analog input channel 6 of group 8 DS6PB AN55 AF7 DSADC: positive analog input of channel 6, pin B I VADCG8.7 D / HighZ / Analog input 50 VDDM VADC analog input channel 7 of group 8 DS6NB AN56 AA4 DSADC: negative analog input channel 6, pin B I D / HighZ / Analog input 56 VDDM VADC analog input channel 0 of group 9 I D / HighZ / Analog input 57 VDDM VADC analog input channel 1 of group 9 (muxtest) I D / HighZ / Analog input 60 VDDM VADC analog input channel 4 of group 9 VADCG9.0 AN57 AB3 VADCG9.1 AN60 Y2 VADCG9.4 DS7PA AN61 AA1 DSADC: positive analog input of channel 7, pin A I VADCG9.5 D / HighZ / Analog input 61 VDDM VADC analog input channel 5 of group 9 DS7NA AN64 W2 DSADC: negative analog input channel 7, pin A I D / HighZ / Analog input 64 VDDM VADC analog input channel 0 of group 10 I D / HighZ / Analog input 65 VDDM VADC analog input channel 1 of group 10 (muxtest) I S/ HighZ / VDDM VADCG10.0 AN65 Y1 VADCG10.1 AN68 V2 VADCG10.4 DS8PA SENT11A Data Sheet Analog input 68 VADC analog input channel 4 of group 10 DSADC: positive analog input of channel 8, pin A SENT input channel 11, pin A TOC-215 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-49 Analog Inputs (cont’d) Pin Symbol Ctrl Type Function W1 AN69 I S/ HighZ / VDDM Analog input 69 VADCG10.5 DS8NA SENT12A AN70 U2 I DS9PA S/ HighZ / VDDM SENT13A AN71 DSADC: negative analog input channel 8, pin A SENT input channel 12, pin A VADCG10.6 V1 VADC analog input channel 5 of group 10 Analog input 70 VADC analog input channel 6 of group 10 DSADC: positive analog input of channel 9, pin A SENT input channel 13, pin A I VADCG10.7 DS9NA S/ HighZ / VDDM SENT14A Analog input 71 VADC analog input channel 7 of group 10 DSADC: negative analog input channel 9, pin A SENT input channel 14, pin A Table 2-50 System I/O Pin Symbol Ctrl Type Function B22 PORST I PORST / PD / VEXT Power On Reset Input Additional strong PD in case of power fail. A23 ESR0 I/O MP / OD / VEXT External System Request Reset 0 Default configuration during and after reset is opendrain driver. The driver drives low during power-on reset. This is valid additionally after deactivation of PORST until the internal reset phase has finished. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. EVRWUP ESR1 A22 EVRWUP I I/O EVR Wakeup Pin External System Request Reset 1 Default NMI function. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. MP / PU1 / VEXT I EVR Wakeup Pin AC17 VGATE1P O VGATE1P / -/ VEXT External Pass Device gate control for EVR13 AC21 VGATE3P O VGATE3P / -/ VEXT External Pass Device gate control for EVR33 F24 TMS I A2 / PD / VDDP3 JTAG Module State Machine Control Input DAP1 Data Sheet I/O Device Access Port Line 1 TOC-216 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-50 System I/O (cont’d) Pin Symbol Ctrl Type Function F23 TRST I A2 / PD / VDDP3 JTAG Module Reset/Enable Input E24 TCK I JTAG Module Clock Input DAP0 I A2 / PD / VDDP3 Device Access Port Line 0 G26 XTAL1 I XTAL1 / -/ VDDP3 Main Oscillator/PLL/Clock Generator Input G25 XTAL2 O XTAL2 / -/ VDDP3 Main Oscillator/PLL/Clock Generator Output Table 2-51 Supply Pin Symbol Ctrl Type Function AD6 VAREF1 I Vx Positive Analog Reference Voltage 1 AC6 VAGND1 I Vx Negative Analog Reference Voltage 1 W4 VAREF2 I Vx Positive Analog Reference Voltage 2 Y4 VAGND2 I Vx Negative Analog Reference Voltage 2 AE9, AE5 VDDM I Vx ADC Analog Power Supply (3.3V / 5V) R1, R4 NC / VDDSB I NCVDD Emulation Device: Emulation SRAM SB Standby Power Supply (1.3V) (Emulation Device only). Production Device: Not Connected. P23, V23, AB23, AC20, B26, C25, D9, D24, E23, H4 VDD I Vx Digital Core Power Supply (1.3V) F26 VDD I Vx Digital Core Power Supply (1.3V). The supply pin inturn supplies the main XTAL Oscillator/PLL (1.3V) . A higher decoupling capacitor is therefore recommended to the VSS pin for better noise immunity. I Vx External Power Supply (5V / 3.3V) I Vx Digital Power Supply for Flash (3.3V). Can be also used as external 3.3V Power Supply for VFLEX. A25, B24, C23, D14, D22, K4, VEXT AC16, AD16, AE16, AF16 H24, H25, H26 Data Sheet VDDP3 TOC-217 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-51 Supply (cont’d) Pin Symbol Ctrl Type Function E26 VDDP3 I Vx Digital Power Supply for Oscillator, LVDSH and A2 pads (3.3V). The supply pin inturn supplies the main XTAL Oscillator/PLL (3.3V) . A higher decoupling capacitor is therefore recommended to the VSS pin for better noise immunity. A18, B18 VDDFL3 I Vx Flash Power Supply (3.3V) D7 VFLEX I Vx Digital Power Supply for Flex Port Pads (5V / 3.3V) AC18, AC22 VFLEXE I Vx Digital Power Supply for EBU Flex Port Pads (5V / 3.3V) M23, T23, Y23 VEBU I Vx Digital Power Supply for EBU (3.3V) AF5, AF9 VSSM I Vx Analog Ground for VDDM AD9 VEVRSB I Vx Standby Power Supply (3.3V/5V) for the Standby SRAM (CPU0.DSPR). If Standby mode is not used: To be handled like VEXT (3.3V/5V). A26, B25, C24, D8, D15, D23, VSS F25, J4, L23, R23, T4, W23, AC19, AC23 I Vx Digital Ground (outer balls) K10, K11, K12, K13, K14, VSS K15, K16, K17, L10, L11, L12, L13, L14, L15, L16, L17 I Vx Digital Ground (center balls) M10, M11, M12, M13, M14, VSS M15, M16, M17, N10, N11, N12, N13, N14, N15, N16, N17 I Vx Digital Ground (center balls) P11, P12, P13, P14, P15, P16, VSS R11, R12, R13, R14, R15, R16 I Vx Digital Ground (center balls) T10, T11, T12, T13, T14, T15, VSS T16, T17, U10, U11, U14, U15, U16, U17 I Vx Digital Ground (center balls) VSS I Vx Digital Ground (center balls) This ball is used in the Emulation Device as AGBT TX0N U12 Data Sheet TOC-218 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: Table 2-51 Supply (cont’d) Pin Symbol Ctrl Type Function U13 VSS I Vx Digital Ground (center balls) This ball is used in the Emulation Device as AGBT TX0P R10 VSS I Vx Digital Ground (center balls) This ball is used in the Emulation Device as AGBT CLKN P10 VSS I Vx Digital Ground (center balls) This ball is used in the Emulation Device as AGBT CLKP R17 VSS I Vx Digital Ground (center balls) This ball is used in the Emulation Device as AGBT ERR P17 NC / VDDPSB I NCVDD Emulation Device: Power Supply (3.3V) PSB for DAP/JTAG pad group. Can be connected to VDDP or can be left unsupplied (see document ´AurixED´ / Aurix Emulation Devices specification. Production Device: This pin is not connected on package level. It can be connected on PCB level to VDDP or Ground or can be left unsupplied. A1, AF1, AF26 NC I NC1 Not Connected. These pins are not connected on package level and will not be used for future extensions. Legend: Column “Ctrl.”: I = Input (for GPIO port Lines with IOCR bit field Selection PCx = 0XXXB) O = Output O0 = Output with IOCR bit field selection PCx = 1X000B O1 = Output with IOCR bit field selection PCx = 1X001B (ALT1) O2 = Output with IOCR bit field selection PCx = 1X010B (ALT2) O3 = Output with IOCR bit field selection PCx = 1X011B (ALT3) O4 = Output with IOCR bit field selection PCx = 1X100B (ALT4) O5 = Output with IOCR bit field selection PCx = 1X101B (ALT5) O6 = Output with IOCR bit field selection PCx = 1X110B (ALT6) O7 = Output with IOCR bit field selection PCx = 1X111B (ALT7) Column “Type”: Data Sheet TOC-219 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: LP = Pad class LP (5V/3.3V, Class LP parameters for digital input / output and class D parameters for analog input function) MP = Pad class MP (5V/3.3V) MP+ = Pad class MP+ (5V/3.3V) MPR = Pad class MPR (5V/3.3V) A2 = Pad class A2 (3.3V) LVDSM = Pad class LVDSM (5V/3.3V) LVDSH = Pad class LVDSH (3.3V) S = Pad class S (Class S parameters for digital input and class D parameters for analog input function) D = Pad class D (VADC / DSADC) PU = with pull-up device connected during reset (PORST = 0) PU1 = with pull-up device connected during reset (PORST = 0)1) 2) 3) PD = with pull-down device connected during reset (PORST = 0) PD1 = with pull-down device connected during reset (PORST = 0)1) 2) 3) PX = Behavior depends on usage: PD in EVR13 SMPS Mode and PU1 in GPIO Mode OD = open drain during reset (PORST = 0) HighZ = tri-state during reset (PORST = 0) PORST = PORST input pad XTAL1 = XTAL1 input pad XTAL2 = XTAL2 input pad VGATE1P = VGATE1P VGATE3P = VGATE3P Vx = Supply NC = These pins are reserved for future extensions and shall not be connected externally NC1 = These pins are not connected on package level and will not be used for future extensions NCVDDPSB = This pin has a different functionality in an Production Device and an Emulation Device. For details pls. see Pin/Ball description of this pin. NCVDDSB = This pin has a different functionality in an Production Device and an Emulation Device. For details pls. see Pin/Ball description of this pin. 2.2.2 Emergency Stop Function The Emergency Stop function can be used to force GPIOs (General Purpose Inputs/Outputs) via an external input signal (EMGSTOPA or EMGSTOPB) into a defined state: • Input state and • PU or High-Z depending on HWCFG[6] level latched during Porst active Control of the Emergency Stop function: • The Emergency Stop function can be enabled/disabled in the SCU (see chapter “SCU”, “Emergency Stop Control”) • The Emergency Stop input signal, EMGSTOPA (P33.8) / EMGSTOPB (P21.2) , can selected in the SCU (see chapter “SCU”, “Emergency Stop Control”) 1) The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG[6] (P14.4). HWCFG[6] has a weak internal pull-up active at start-up if the pin is left unconnected.See also User´s Manual, “Introduction Chapter”, “General Purpose I/O Ports and Peripheral I/O Lines”, Figure: “Default state of port pins during and after reset”. 2) If HWCFG[6] is left unconnected or is externally pulled high, weak internal pull-ups (PU1) / pull-downs (PD1) are active during and after reset. 3) If HWCFG[6] is connected to ground, the PD1 / PU1 pins are predominantly in HighZ during and after reset. Data Sheet TOC-220 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC298x Pin Definition and Functions: • On port level, each GPIO can be enabled/disabled for the Emergency Stop function via the Px_ESR (Port x Emergency Stop) registers in the port control logic (see chapter “General Purpose I/O Ports and Peripheral I/O Lines”, “Emergency Stop Register”). The Emergency Stop function is available for all GPIO Ports with the following exceptions: • Not available for P20.2 (General Purpose Input/GPI only, overlayed with Testmode) • Not available for P40.x (analoge input ANx overlayed with GPI) • Not available for P32.0 EVR13 SMPS mode. • Not available for dedicated I/O without General Purpose Output function (e.g ESRx, TMS, TCK) The Emergency Stop function can be overruled on the following GPIO Ports: • P00.x and P02.x: Emergency Stop can be overruled by the 8-Bit Standby Controller (SBR), if implemented. Overruling can be disabled via the control registers P00_SCR / P02_SCR (see chapter “General Purpose I/O Ports and Peripheral I/O Lines”, P00 / P01) • P00.x: Emergency Stop can be overruled by the VADC. Overruling can be disabled via the control register P00_SCR (see chapter “General Purpose I/O Ports and Peripheral I/O Lines”, P00) • P14.0 and P14.1: Emergency Stop can be overruled in the DXCPL mode (DAP over can physical layer mode). No Overruling in the DXCM (Debug over can message) mode • P21.6: Emergency Stop can be overruled in JTAG mode if this pin is used as TDI • P21.7: Emergency Stop can be overruled in JTAG or Three Pin DAP mode • P20.0: Emergency Stop can be overruled in JTAG mode if this GPIO is used as TDI • P33.8: Emergency Stop can be overruled if this pin is used as safety output pin (SMUFSP) 2.2.3 Pull-Up/Pull-Down Reset Behavior of the Pins Table 2-52 List of Pull-Up/Pull-Down Reset Behavior of the Pins Pins PORST = 0 all GPIOs Pull-up if HWCFG[6] = 1 or High-Z if HWCFG[6] = 0 TDI, TESTMODE Pull-up 1) PORST Pull-down with IPORST relevant TRST, TCK, TMS Pull-down ESR0 The open-drain driver is used to drive low.2) ESR1 Pull-up3) TDO Pull-up 1) 2) 3) 4) PORST = 1 Pull-down with IPDLI relevant Pull-up3) High-Z/Pull-up4) Pull-down with IPORST relevant is always activated when a primary supply monitor detects a violation. Valid additionally after deactivation of PORST until the internal reset phase has finished. See the SCU chapter for details. See the SCU_IOCR register description. Depends on JTAG/DAP selection with TRST. In case of leakage test (PORST = 0 and TESTMODE = 0), the pull-down of the TRST pin is switched off. In case of an user application (TESTMODE = 1), the pull-down of the TRST is always switched on. Data Sheet TOC-221 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: 2.3 TC297x Pin Definition and Functions: BGA292 Figure 2-3 is showing the TC297x Logic Symbol for the package variant: BGA292. 20 19 18 17 16 15 14 13 12 11 10 9 8 7 Y VSS P32.3 P32.2 P32.0 P33.13 P33.11 P33.9 P33.7 P33.5 P33.3 P33.1 AN5 AN10 W VEXT VSS P32.4 VGATE1 P33.12 P P33.10 P33.8 P33.6 P33.4 P33.2 P33.0 AN2 AN8 AN11 V P23.0 VEXT 6 5 4 3 2 1 VDDM VSSM AN20 AN21 NC Y AN13 AN16 AN18 AN19 AN24 AN25 W AN26 AN27 V AN28 AN29 U VAGND1 VAREF1 17 16 15 14 13 12 11 10 9 8 7 6 5 4 U P23.2 P23.1 U VSS P32.7 P32.6 P33.15 P34.5 P34.3 P34.1 AN1 AN3 AN7 AN9 AN14 AN17 NC U T P23.4 P23.3 T P23.5 VSS P32.5 P33.14 P34.4 P34.2 VEVRSB AN0 AN4 AN6 AN12 AN15 AN22 AN30 T R P22.2 P22.3 R P23.6 P23.7 AN23 AN31 R AN35 AN33 R VSS VSS (AGBT TX0P) VSS (AGBT TX0N) VSS AN34 AN32 P AN37 AN39 P VSS VSS VSS VSS VDD AN38 AN36 N AN45 AN44 N VSS VSS VSS VSS AN40 AN41 M AN47 AN46 M AN43 L P00.12 P00.11 L Top-View VDD P P22.0 P22.1 P P22.5 P22.4 N VDDP3 VDD N P22.7 P22.6 VDD M XTAL1 XTAL2 M P22.9 P22.8 VSS VSS L VSS TRST L P22.11 P22.10 VSS (AGBT ERR) VSS VSS VSS VSS VSS VSS VSS (AGBT CLKN) AN42 K P21.4 P21.2 K P21.0 TMS NC (VDDPSB) VSS VSS VSS VSS VSS VSS VSS (AGBT CLKP) P00.10 P00.8 K P00.9 P00.7 K J P21.5 P21.3 J P21.1 TCK VSS VSS VSS VSS VSS VSS P01.7 P00.6 J P00.5 P00.4 J H P20.0 P20.2 H P21.6 P21.7 VDD VSS VSS VSS VSS VDD (VDDSB) P01.5 P01.6 H P00.3 P00.2 H G P20.3 P20.1 G PORST ESR1 VSS VSS VSS VSS P01.3 P01.4 G P00.1 P00.0 G F P20.8 P20.7 F P20.6 ESR0 P02.10 P02.11 F P02.7 P02.8 F E P20.11 P20.10 E P20.9 VSS VDDFL3 P15.5 P14.2 P12.0 P12.1 P11.0 P11.1 P11.7 P11.8 P11.13 VSS P02.9 E P02.5 P02.6 E D P20.13 P20.12 D VSS VDDFL3 P15.7 P15.8 P14.7 P14.9 P14.10 P11.4 P11.6 P11.5 P11.14 P11.15 VFLEX VSS P02.3 P02.4 D 17 16 15 14 13 12 11 10 9 8 7 6 5 4 C P20.14 P15.2 P02.1 P02.2 C B P15.0 VSS VDDP3 P15.3 P14.0 P14.4 P14.3 P14.6 P13.0 P13.2 P11.3 P11.10 P11.12 P10.1 P10.4 P10.5 P10.8 VEXT VSS P02.0 B A VSS VDDP3 P15.1 P15.4 P15.6 P14.1 P14.5 P14.8 P13.1 P13.3 P11.2 P11.9 P11.11 P10.0 P10.3 P10.2 P10.6 P10.7 VEXT NC A 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VDD VDD VAGND2 VAREF2 T VDD (VDDSB) D Figure 2-3 TC297x Logic Symbol for the package variant BGA292. Data Sheet TOC-222 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: 2.3.1 TC297x BGA292 Package Variant Pin Configuration Table 2-53 Port 00 Functions Pin Symbol Ctrl Type Function G1 P00.0 I MP / PU1 / VEXT General-purpose input TIN9 CTRAPA GTM input CCU61 input T12HRE CCU60 input INJ00 MSC0 input CIFD9 CIF input P00.0 O0 General-purpose output TOUT9 O1 GTM output ASCLK3 O2 ASCLIN3 output ATX3 O3 ASCLIN3 output – O4 Reserved TXDCAN1 O5 CAN node 1 output – O6 Reserved COUT63 O7 CCU60 output ETHMDIOA HWOU T ETH input/output Data Sheet TOC-223 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-53 Port 00 Functions (cont’d) Pin Symbol Ctrl Type Function G2 P00.1 I LP / PU1 / VEXT General-purpose input TIN10 ARX3E H1 GTM input ASCLIN3 input RXDCAN1D CAN node 1 input PSIRX0A PSI5 input SENT0B SENT input CC60INB CCU60 input CC60INA CCU61 input DSCIN5A DSADC channel 5 input DS5NA DSADC positive analog input of channel channel 5, pin A DSCIN7B DSADC channel 7 input VADCG7.5 VADC analog input channel 5 of group 7 CIFD10 CIF input P00.1 O0 General-purpose output TOUT10 O1 GTM output ATX3 O2 ASCLIN3 output – O3 Reserved DSCOUT5 O4 DSADC channel 5 output DSCOUT7 O5 DSADC channel 7 output SPC0 O6 SENT output CC60 O7 CCU61 output P00.2 I TIN11 SENT1B LP / PU1 / VEXT General-purpose input GTM input SENT input DSDIN5A DSADC channel 5 input DSDIN7B DSADC channel 7 input DS5PA DSADC negative analog input of channel 5, pin A VADCG7.4 VADC analog input channel 4 of group 7 CIFD11 CIF input P00.2 O0 General-purpose output TOUT11 O1 GTM output ASCLK3 O2 ASCLIN3 output TXDCANr1 O3 CAN node 1 output (MultiCANr+) PSITX0 O4 PSI5 output TXDCAN3 O5 CAN node 3 output SLSO34 O6 QSPI3 output COUT60 O7 CCU61 output Data Sheet TOC-224 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-53 Port 00 Functions (cont’d) Pin Symbol Ctrl Type Function H2 P00.3 I LP / PU1 / VEXT General-purpose input TIN12 RXDCAN3A J1 GTM input CAN node 3 input RXDCANr1A CAN node 1 input (MultiCANr+) PSIRX1A PSI5 input PSISRXA PSI5-S input SENT2B SENT input CC61INB CCU60 input CC61INA CCU61 input DSCIN3A DSADC channel 3 input VADCG7.3 VADC analog input channel 3 of group 7 DSITR5F DSADC channel 5 input CIFD12 CIF input P00.3 O0 General-purpose output TOUT12 O1 GTM output ASLSO3 O2 ASCLIN3 output – O3 Reserved DSCOUT3 O4 DSADC channel 3 output – O5 Reserved SPC2 O6 SENT output CC61 O7 CCU61 output P00.4 I TIN13 REQ7 LP / PU1 / VEXT General-purpose input GTM input SCU input SENT3B SENT input DSDIN3A DSADC channel 3 input DSSGNA DSADC channel input VADCG7.2 VADC analog input channel 2 of group 7 CIFD13 CIF input P00.4 O0 General-purpose output TOUT13 O1 GTM output PSISTX O2 PSI5-S output – O3 Reserved PSITX1 O4 PSI5 output VADCG4BFL0 O5 VADC output SPC3 O6 SENT output COUT61 O7 CCU61 output Data Sheet TOC-225 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-53 Port 00 Functions (cont’d) Pin Symbol Ctrl Type Function J2 P00.5 I LP / PU1 / VEXT General-purpose input TIN14 PSIRX2A J4 GTM input PSI5 input SENT4B SENT input CC62INB CCU60 input CC62INA CCU61 input DSCIN2A DSADC channel 2 input VADCG7.1 VADC analog input channel 1 of group 7 CIFD14 CIF input P00.5 O0 General-purpose output TOUT14 O1 GTM output DSCGPWMN O2 DSADC output SLSO33 O3 QSPI3 output DSCOUT2 O4 DSADC channel 2 output VADCG4BFL1 O5 VADC output SPC4 O6 SENT output CC62 O7 CCU61 output P00.6 I TIN15 SENT5B LP / PU1 / VEXT General-purpose input GTM input SENT input DSDIN2A DSADC channel 2 input A VADCG7.0 VADC analog input channel 0 of group 7 (with pull down diagnostics) DSITR4F DSADC channel 4 input F CIFD15 CIF input P00.6 O0 General-purpose output TOUT15 O1 GTM output DSCGPWMP O2 DSADC output VADCG4BFL2 O3 VADC output PSITX2 O4 PSI5 output VADCEMUX10 O5 VADC output SPC5 O6 SENT output COUT62 O7 CCU61 output Data Sheet TOC-226 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-53 Port 00 Functions (cont’d) Pin Symbol Ctrl Type Function K1 P00.7 I LP / PU1 / VEXT General-purpose input TIN16 SENT6B K4 GTM input SENT input CC60INC CCU61 input CCPOS0A CCU61 input T12HRB CCU60 input T2INA GPT120 input DSCIN4A DSADC channel 4 input A DS4NA DSADC negative analog input channel 4, pin A VADCG6.5 VADC analog input channel 5 of group 6 CIFCLK CIF input P00.7 O0 General-purpose output TOUT16 O1 GTM output – O2 Reserved VADCG4BFL3 O3 VADC output DSCOUT4 O4 DSADC channel 4 output VADCEMUX11 O5 VADC output SPC6 O6 SENT output CC60 O7 CCU61 output P00.8 I TIN17 SENT7B LP / PU1 / VEXT General-purpose input GTM input SENT input CC61INC CCU61 input CCPOS1A CCU61 input T13HRB CCU60 input T2EUDA GPT120 input DSDIN4A DSADC channel 4 input A DS4PA DSADC positive analog input of channel 4, pin A VADCG6.4 VADC analog input channel 4 of group 6 CIFVSNC CIF input P00.8 O0 General-purpose output TOUT17 O1 GTM output SLSO36 O2 QSPI3 output – O3 Reserved – O4 Reserved VADCEMUX12 O5 VADC output SPC7 O6 SENT output CC61 O7 CCU61 output Data Sheet TOC-227 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-53 Port 00 Functions (cont’d) Pin Symbol Ctrl Type Function K2 P00.9 I LP / PU1 / VEXT General-purpose input TIN18 SENT8B K5 GTM input SENT input CC62INC CCU61 input CCPOS2A CCU61 input T13HRC CCU60 input T12HRC CCU60 input T4EUDA GPT120 input DSCIN1A DSADC channel 1 input A VADCG6.3 VADC analog input channel 3 of group 6 DSITR3F DSADC channel 3 input F CIFHSNC CIF input P00.9 O0 General-purpose output TOUT18 O1 GTM output SLSO37 O2 QSPI3 output ARTS3 O3 ASCLIN3 output DSCOUT1 O4 DSADC channel 1 output – O5 Reserved SPC8 O6 SENT output CC62 O7 CCU61 output P00.10 I TIN19 SENT9B LP / PU1 / VEXT General-purpose input GTM input SENT input DSDIN1A DSADC channel 1 input A VADCG6.2 VADC analog input channel 2 of group 6 P00.10 O0 General-purpose output TOUT19 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved SPC9 O6 SENT output COUT63 O7 CCU61 output Data Sheet TOC-228 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-53 Port 00 Functions (cont’d) Pin Symbol Ctrl Type Function L1 P00.11 I LP / PU1 / VEXT General-purpose input TIN20 CTRAPA L2 GTM input CCU60 input T12HRE CCU61 input DSCIN0A DSADC channel 0 input A VADCG6.1 VADC analog input channel 1 of group 6 P00.11 O0 General-purpose output TOUT20 O1 GTM output – O2 Reserved – O3 Reserved DSCOUT0 O4 DSADC channel 0 output – O5 Reserved – O6 Reserved – O7 Reserved P00.12 I TIN21 ACTS3A LP / PU1 / VEXT General-purpose input GTM input ASCLIN3 input DSDIN0A DSADC channel 0 input A VADCG6.0 VADC analog input channel 0 of group 6 P00.12 O0 General-purpose output TOUT21 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved COUT63 O7 CCU61 output Data Sheet TOC-229 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-54 Port 01 Functions Pin Symbol Ctrl Type Function G5 P01.3 I LP / PU1 / VEXT General-purpose input TIN111 SLSI3B DSITR7F G4 QSPI3 input DSADC channel 7 input F P01.3 O0 General-purpose output TOUT111 O1 GTM output – O2 Reserved – O3 Reserved SLSO39 O4 QSPI3 output TXDCAN1 O5 CAN node 1 output – O6 Reserved – O7 Reserved P01.4 I TIN112 RXDCAN1C LP / PU1 / VEXT DSITR7E H5 GTM input General-purpose input GTM input CAN node 1 input DSADC channel 7 input E P01.4 O0 General-purpose output TOUT112 O1 GTM output – O2 Reserved – O3 Reserved SLSO310 O4 QSPI3 output – O5 Reserved – O6 Reserved – O7 Reserved P01.5 I TIN113 MRST3C DSCIN8A LP / PU1 / VEXT General-purpose input GTM input QSPI3 input DSADC channel 8 input A P01.5 O0 General-purpose output TOUT113 O1 GTM output – O2 Reserved – O3 Reserved MRST3 O4 QSPI3 output – O5 Reserved DSCOUT8 O6 DSADC channel 8 output – O7 Reserved Data Sheet TOC-230 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-54 Port 01 Functions (cont’d) Pin Symbol Ctrl Type Function H4 P01.6 I MP / PU1 / VEXT General-purpose input TIN114 MTSR3C DSDIN8A J5 GTM input QSPI3 input DSADC channel 8 input A P01.6 O0 General-purpose output TOUT114 O1 GTM output – O2 Reserved – O3 Reserved MTSR3 O4 QSPI3 output – O5 Reserved – O6 Reserved – O7 Reserved P01.7 I TIN115 SCLK3C DSITR8F MP / PU1 / VEXT General-purpose input GTM input QSPI3 input DSADC channel 8 input F P01.7 O0 General-purpose output TOUT115 O1 GTM output – O2 Reserved – O3 Reserved SCLK3 O4 QSPI3 output – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-231 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-55 Port 02 Functions Pin Symbol Ctrl Type Function B1 P02.0 I MP+ / PU1 / VEXT General-purpose input TIN0 REQ6 C2 GTM input SCU input ARX2G ASCLIN2 input CC60INA CCU60 input CC60INB CCU61 input CIFD0 CIF input P02.0 O0 General-purpose output TOUT0 O1 GTM output ATX2 O2 ASCLIN2 output SLSO31 O3 QSPI3 output DSCGPWMN O4 DSADC output TXDCAN0 O5 CAN node 0 output TXD0A O6 ERAY0 output CC60 O7 CCU60 output P02.1 I TIN1 LP / PU1 General-purpose input / VEXT GTM input REQ14 SCU input ARX2B ASCLIN2 input RXDCAN0A CAN node 0 input RXD0A2 ERAY0 input CIFD1 CIF input P02.1 O0 General-purpose output TOUT1 O1 GTM output SLSO47 O2 QSPI4 output SLSO32 O3 QSPI3 output DSCGPWMP O4 DSADC output – O5 Reserved – O6 Reserved COUT60 O7 CCU60 output Data Sheet TOC-232 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-55 Port 02 Functions (cont’d) Pin Symbol Ctrl Type Function C1 P02.2 I MP+ / PU1 / VEXT General-purpose input TIN2 CC61INA D2 GTM input CCU60 input CC61INB CCU61 input CIFD2 CIF input P02.2 O0 General-purpose output TOUT2 O1 GTM output ATX1 O2 ASCLIN1 output SLSO33 O3 QSPI3 output PSITX0 O4 PSI5 output TXDCAN2 O5 CAN node 2 output TXD0B O6 ERAY0 output CC61 O7 CCU60 output P02.3 I TIN3 ARX1G LP / PU1 / VEXT General-purpose input GTM input ASCLIN1 input RXDCAN2B CAN node 2 input RXD0B2 ERAY0 input PSIRX0B PSI5 input DSCIN5B DSADC channel 5 input B SDI11 MSC1 input CIFD3 CIF input P02.3 O0 General-purpose output TOUT3 O1 GTM output ASLSO2 O2 ASCLIN2 output SLSO34 O3 QSPI3 output DSCOUT5 O4 DSADC channel 5 output – O5 Reserved – O6 Reserved COUT61 O7 CCU60 output Data Sheet TOC-233 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-55 Port 02 Functions (cont’d) Pin Symbol Ctrl Type Function D1 P02.4 I MP+ / PU1 / VEXT General-purpose input TIN4 SLSI3A E2 GTM input QSPI3 input ECTT1 TTCAN input RXDCAN0D CAN node 0 input CC62INA CCU60 input CC62INB CCU61 input DSDIN5B DSADC channel 5 input B SDA0A I2C0 input CIFD4 CIF input P02.4 O0 General-purpose output TOUT4 O1 GTM output ASCLK2 O2 ASCLIN2 output SLSO30 O3 QSPI3 output PSISCLK O4 PSI5-S output SDA0 O5 I2C0 output TXEN0A O6 ERAY0 output CC62 O7 CCU60 output P02.5 I TIN5 MRST3A MP+ / PU1 / VEXT General-purpose input GTM input QSPI3 input ECTT2 TTCAN input PSIRX1B PSI5 input PSISRXB PSI5-S input SENT3C SENT input DSCIN4B DSADC channel 4 input B SCL0A I2C0 input CIFD5 CIF input P02.5 O0 General-purpose output TOUT5 O1 GTM output TXDCAN0 O2 CAN node 0 output MRST3 O3 QSPI3 output DSCOUT4 O4 DSADC channel 4 output SCL0 O5 I2C0 output TXEN0B O6 ERAY0 output COUT62 O7 CCU60 output Data Sheet TOC-234 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-55 Port 02 Functions (cont’d) Pin Symbol Ctrl Type Function E1 P02.6 I MP / PU1 / VEXT General-purpose input TIN6 MTSR3A GTM input QSPI3 input SENT2C SENT input CC60INC CCU60 input CCPOS0A CCU60 input T12HRB CCU61 input T3INA GPT120 input CIFD6 CIF input DSDIN4B DSADC channel 4 input B DSITR5E DSADC channel 5 input E P02.6 O0 General-purpose output TOUT6 O1 GTM output PSISTX O2 PSI5-S output MTSR3 O3 QSPI3 output PSITX1 O4 PSI5 output VADCEMUX00 O5 VADC output – O6 Reserved CC60 O7 CCU60 output Data Sheet TOC-235 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-55 Port 02 Functions (cont’d) Pin Symbol Ctrl Type Function F2 P02.7 I MP / PU1 / VEXT General-purpose input TIN7 SCLK3A GTM input QSPI3 input PSIRX2B PSI5 input SENT1C SENT input CC61INC CCU60 input CCPOS1A CCU60 input T13HRB CCU61 input T3EUDA GPT120 input CIFD7 CIF input DSCIN3B DSADC channel 3 input B DSITR4E DSADC channel 4 input E P02.7 O0 General-purpose output TOUT7 O1 GTM output – O2 Reserved SCLK3 O3 QSPI3 output DSCOUT3 O4 DSADC channel 3 output VADCEMUX01 O5 VADC output SPC1 O6 SENT output CC61 O7 CCU60 output Data Sheet TOC-236 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-55 Port 02 Functions (cont’d) Pin Symbol Ctrl Type F1 P02.8 I SENT0C LP / PU1 General-purpose input / GTM input VEXT SENT input CC62INC CCU60 input CCPOS2A CCU60 input T12HRC CCU61 input T13HRC CCU61 input T4INA GPT120 input CIFD8 CIF input DSDIN3B DSADC channel 3 input B DSITR3E DSADC channel 3 input E TIN8 E4 Function P02.8 O0 General-purpose output TOUT8 O1 GTM output SLSO35 O2 QSPI3 output – O3 Reserved PSITX2 O4 PSI5 output VADCEMUX02 O5 VADC output ETHMDC O6 ETH output CC62 O7 CCU60 output P02.9 I TIN116 LP / PU1 / VEXT General-purpose input GTM input P02.9 O0 TOUT116 O1 GTM output ATX2 O2 ASCLIN2 output – O3 Reserved – O4 Reserved TXDCAN1 O5 CAN node 1 output – O6 Reserved – O7 Reserved Data Sheet General-purpose output TOC-237 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-55 Port 02 Functions (cont’d) Pin Symbol Ctrl Type Function F5 P02.10 I LP / PU1 / VEXT General-purpose input TIN117 ARX2C RXDCAN1E F4 GTM input ASCLIN2 input CAN node 1 input P02.10 O0 General-purpose output TOUT117 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P02.11 I TIN118 LP / PU1 / VEXT General-purpose input GTM input P02.11 O0 General-purpose output TOUT118 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Table 2-56 Port 10 Functions Pin Symbol Ctrl Type Function A7 P10.0 I LP / PU1 / VEXT General-purpose input TIN102 T6EUDB GTM input GPT120 input P10.0 O0 General-purpose output TOUT102 O1 GTM output – O2 Reserved SLSO110 O3 QSPI1 output – O4 Reserved VADCG6BFL0 O5 VADC output – O6 Reserved – O7 Reserved Data Sheet TOC-238 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-56 Port 10 Functions (cont’d) Pin Symbol Ctrl Type Function B7 P10.1 I MP+ / PU1 / VEXT General-purpose input TIN103 MRST1A T5EUDB A5 GTM input QSPI1 input GPT120 input P10.1 O0 General-purpose output TOUT103 O1 GTM output MTSR1 O2 QSPI1 output MRST1 O3 QSPI1 output EN01 O4 MSC0 output VADCG6BFL1 O5 VADC output END03 O6 MSC0 output – O7 Reserved P10.2 I TIN104 SCLK1A MP / PU1 / VEXT General-purpose input GTM input QSPI1 input T6INB GPT120 input REQ2 SCU input RXDCAN2E CAN node 2 input SDI01 MSC0 input P10.2 O0 General-purpose output TOUT104 O1 GTM output – O2 Reserved SCLK1 O3 QSPI1 output EN00 O4 MSC0 output VADCG6BFL2 O5 VADC output END02 O6 MSC0 output – O7 Reserved Data Sheet TOC-239 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-56 Port 10 Functions (cont’d) Pin Symbol Ctrl Type Function A6 P10.3 I MP / PU1 / VEXT General-purpose input TIN105 MTSR1A B6 GTM input QSPI1 input REQ3 SCU input T5INB GPT120 input P10.3 O0 General-purpose output TOUT105 O1 GTM output VADCG6BFL3 O2 VADC output MTSR1 O3 QSPI1 output EN00 O4 MSC0 output END02 O5 MSC0 output TXDCAN2 O6 CAN node 2 output – O7 Reserved P10.4 I TIN106 MTSR1C MP+ / PU1 / VEXT General-purpose input GTM input QSPI1 input CCPOS0C CCU60 input T3INB GPT120 input P10.4 O0 General-purpose output TOUT106 O1 GTM output – O2 Reserved SLSO18 O3 QSPI1 output MTSR1 O4 QSPI1 output EN00 O5 MSC0 output END02 O6 MSC0 output – O7 Reserved Data Sheet TOC-240 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-56 Port 10 Functions (cont’d) Pin Symbol Ctrl Type Function B5 P10.5 I LP / PU1 / VEXT General-purpose input TIN107 HWCFG4 A4 GTM input SCU input RXDCANr0A CAN node 0 input (MultiCANr+) INJ01 MSC0 input P10.5 O0 General-purpose output TOUT107 O1 GTM output ATX2 O2 ASCLIN2 output SLSO38 O3 QSPI3 output SLSO19 O4 QSPI1 output T6OUT O5 GPT120 output ASLSO2 O6 ASCLIN2 output PSITX3 O7 PSI5 output P10.6 I TIN108 ARX2D LP / PU1 / VEXT General-purpose input GTM input ASCLIN2 input MTSR3B QSPI3 input PSIRX3C PSI5 input HWCFG5 SCU input P10.6 O0 General-purpose output TOUT108 O1 GTM output ASCLK2 O2 ASCLIN2 output MTSR3 O3 QSPI3 output T3OUT O4 GPT120 output TXDCANr0 O5 CAN node 0 output (MultiCANr+) MRST1 O6 QSPI1 output VADCG7BFL0 O7 VADC output Data Sheet TOC-241 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-56 Port 10 Functions (cont’d) Pin Symbol Ctrl Type Function A3 P10.7 I LP / PU1 / VEXT General-purpose input TIN109 ACTS2A B4 GTM input ASCLIN2 input MRST3B QSPI3 input REQ4 SCU input CCPOS1C CCU60 input T3EUDB GPT120 input P10.7 O0 General-purpose output TOUT109 O1 GTM output – O2 Reserved MRST3 O3 QSPI3 output VADCG7BFL1 O4 VADC output TXDCANr0 O5 CAN node 0 output (MultiCANr+) – O6 Reserved – O7 Reserved P10.8 I TIN110 SCLK3B LP / PU1 / VEXT General-purpose input GTM input QSPI3 input REQ5 SCU input CCPOS2C CCU60 input T4INB GPT120 input RXDCANr0B CAN node 0 input (MultiCANr+) P10.8 O0 General-purpose output TOUT110 O1 GTM output ARTS2 O2 ASCLIN2 output SCLK3 O3 QSPI3 output – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-242 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-57 Port 11 Functions Pin Symbol Ctrl Type Function E10 P11.0 I MP+ / PU1 / VFLEX General-purpose input TIN119 ARX3B E9 ASCLIN3 input P11.0 O0 General-purpose output TOUT119 O1 GTM output ATX3 O2 ASCLIN3 output – O3 Reserved – O4 Reserved – O5 Reserved ETHTXD3 O6 ETH output – O7 Reserved P11.1 I TIN120 A10 GTM input MP+ / PU1 / VFLEX General-purpose input GTM input P11.1 O0 TOUT120 O1 GTM output ASCLK3 O2 ASCLIN3 output ATX3 O3 ASCLIN3 output – O4 Reserved – O5 Reserved ETHTXD2 O6 ETH output – O7 Reserved P11.2 I TIN95 MPR/ PU1 / VFLEX General-purpose output General-purpose input GTM input P11.2 O0 TOUT95 O1 GTM output END03 O2 MSC0 output SLSO05 O3 QSPI0 output SLSO15 O4 QSPI1 output EN01 O5 MSC0 output ETHTXD1 O6 ETH output COUT63 O7 CCU60 output Data Sheet General-purpose output TOC-243 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-57 Port 11 Functions (cont’d) Pin Symbol Ctrl Type Function B10 P11.3 I MPR / PU1 / VFLEX General-purpose input TIN96 MRST1B SDI03 D10 QSPI1 input MSC0 input P11.3 O0 General-purpose output TOUT96 O1 GTM output – O2 Reserved MRST1 O3 QSPI1 output TXD0A O4 ERAY0 output – O5 Reserved ETHTXD0 O6 ETH output COUT62 O7 CCU60 output P11.4 I TIN121 ETHRXCLKB D8 GTM input MP+ / PU1 / VFLEX General-purpose input GTM input ETH input P11.4 O0 General-purpose output TOUT121 O1 GTM output ASCLK3 O2 ASCLIN3 output – O3 Reserved – O4 Reserved – O5 Reserved ETHTXER O6 ETH output – O7 Reserved P11.5 I TIN122 ETHTXCLKA LP / PU1 / VFLEX General-purpose input GTM input ETH input P11.5 O0 General-purpose output TOUT122 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-244 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-57 Port 11 Functions (cont’d) Pin Symbol Ctrl Type Function D9 P11.6 I MPR / PU1 / VFLEX General-purpose input TIN97 SCLK1B E8 QSPI1 input P11.6 O0 General-purpose output TOUT97 O1 GTM output TXEN0B O2 ERAY0 output SCLK1 O3 QSPI1 output TXEN0A O4 ERAY0 output FCLP0 O5 MSC0 output ETHTXEN O6 ETH output COUT61 O7 CCU60 output P11.7 I TIN123 ETHRXD3 E7 GTM input LP / PU1 / VFLEX General-purpose input GTM input ETH input P11.7 O0 General-purpose output TOUT123 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P11.8 I TIN124 ETHRXD2 LP / PU1 / VFLEX General-purpose input GTM input ETH input P11.8 O0 General-purpose output TOUT124 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-245 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-57 Port 11 Functions (cont’d) Pin Symbol Ctrl Type Function A9 P11.9 I MP+ / PU1 / VFLEX General-purpose input TIN98 MTSR1B B9 GTM input QSPI1 input RXD0A1 ERAY0 input ETHRXD1 ETH input P11.9 O0 General-purpose output TOUT98 O1 GTM output – O2 Reserved MTSR1 O3 QSPI1 output – O4 Reserved SOP0 O5 MSC0 output – O6 Reserved COUT60 O7 CCU60 output P11.10 I TIN99 REQ12 LP / PU1 / VFLEX General-purpose input GTM input SCU input ARX1E ASCLIN1 input SLSI1A QSPI1 input RXDCAN3D CAN node 3 input RXD0B1 ERAY0 input ETHRXD0 ETH input SDI00 MSC0 input P11.10 O0 General-purpose output TOUT99 O1 GTM output – O2 Reserved SLSO03 O3 QSPI0 output SLSO13 O4 QSPI1 output – O5 Reserved – O6 Reserved CC62 O7 CCU60 output Data Sheet TOC-246 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-57 Port 11 Functions (cont’d) Pin Symbol Ctrl Type Function A8 P11.11 I MP+ / PU1 / VFLEX General-purpose input TIN100 ETHCRSDVA B8 GTM input ETH input ETHRXDVA ETH input ETHCRSB ETH input P11.11 O0 General-purpose output TOUT100 O1 GTM output END02 O2 MSC0 output SLSO04 O3 QSPI0 output SLSO14 O4 QSPI1 output EN00 O5 MSC0 output TXEN0B O6 ERAY0 output CC61 O7 CCU60 output P11.12 I TIN101 ETHREFCLK MPR / PU1 / VFLEX General-purpose input GTM input ETH input ETHTXCLKB ETH input (Not for productive purposes) ETHRXCLKA ETH input (Not for productive purposes) P11.12 O0 General-purpose output TOUT101 O1 GTM output ATX1 O2 ASCLIN1 output GTMCLK2 O3 GTM output TXD0B O4 ERAY0 output TXDCAN3 O5 CAN node 3 output EXTCLK1 O6 SCU output CC60 O7 CCU60 output Data Sheet TOC-247 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-57 Port 11 Functions (cont’d) Pin Symbol Ctrl Type Function E6 P11.13 I LP / PU1 / VFLEX General-purpose input TIN125 ETHRXERA SDA1A D7 ETH input I2C1 input P11.13 O0 General-purpose output TOUT125 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved SDA1 O6 I2C1 output – O7 Reserved P11.14 I TIN126 ETHCRSDVB D6 GTM input LP / PU1 / VFLEX General-purpose input GTM input ETH input ETHRXDVB ETH input ETHCRSA ETH input SCL1A I2C1 input P11.14 O0 General-purpose output TOUT126 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved SCL1 O6 I2C1 output – O7 Reserved P11.15 I TIN127 ETHCOL LP / PU1 / VFLEX General-purpose input GTM input ETH input P11.15 O0 General-purpose output TOUT127 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-248 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-58 Port 12 Functions Pin Symbol Ctrl Type Function E12 P12.0 I LP / PU1 / VFLEX General-purpose input TIN128 ETHRXCLKC RXDCAN0C GTM input ETH input CAN node 0 input P12.0 O0 General-purpose output TOUT128 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved ETHMDC O6 ETH output – O7 Reserved P12.1 E11 I TIN129 LP / PU1 / VFLEX General-purpose input GTM input P12.1 O0 General-purpose output TOUT129 O1 GTM output ASLSO3 O2 ASCLIN3 output – O3 Reserved – O4 Reserved TXDCAN0 O5 CAN node 0 output – O6 Reserved – O7 Reserved ETHMDIOC HWOU T ETH input/output Table 2-59 Port 13 Functions Pin Symbol Ctrl Type Function B12 P13.0 I LVDSM_N / PU1 / VEXT General-purpose input TIN91 GTM input P13.0 O0 TOUT91 O1 GTM output END03 O2 MSC0 output SCLK2N O3 QSPI2 output (LVDS) EN01 O4 MSC0 output FCLN0 O5 MSC0 output (LVDS) FCLND0 O6 MSC0 output (LVDS) – O7 Reserved Data Sheet TOC-249 General-purpose output V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-59 Port 13 Functions (cont’d) Pin Symbol Ctrl Type Function A12 P13.1 I LVDSM_P / PU1 / VEXT General-purpose input TIN92 SCL0B GTM input I2C0 input P13.1 O0 General-purpose output TOUT92 O1 GTM output – O2 Reserved SCLK2P O3 QSPI2 output (LVDS) – O4 Reserved FCLP0 O5 MSC0 output (LVDS) SCL0 O6 I2C0 output – O7 Reserved P13.2 B11 I TIN93 CAPINA LVDSM_N / PU1 / VEXT SDA0B General-purpose input GTM input GPT120 input I2C0 input P13.2 O0 General-purpose output TOUT93 O1 GTM output – O2 Reserved MTSR2N O3 QSPI2 output (LVDS) FCLP0 O4 MSC0 output SON0 O5 MSC0 output (LVDS) SDA0 O6 I2C0 output SOND0 O7 MSC0 output (LVDS) P13.3 A11 I TIN94 LVDSM_P / PU1 / VEXT General-purpose input GTM input P13.3 O0 TOUT94 O1 GTM output – O2 Reserved MTSR2P O3 QSPI2 output (LVDS) – O4 Reserved SOP0 O5 MSC0 output (LVDS) – O6 Reserved – O7 Reserved Data Sheet TOC-250 General-purpose output V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-60 Port 14 Functions Pin Symbol Ctrl Type Function B16 P14.0 I MP+ / PU1 / VEXT General-purpose input TIN80 SENT12D GTM input SENT input P14.0 O0 General-purpose output TOUT80 O1 GTM output ATX0 O2 ASCLIN0 output Recommended as Boot loader pin TXD0A O3 ERAY0 output TXD0B O4 ERAY0 output TXDCAN1 O5 CAN node 1 output Used for single pin DAP (SPD) function ASCLK0 O6 ASCLIN0 output COUT62 O7 CCU60 output P14.1 A15 I TIN81 REQ15 MP / PU1 / VEXT General-purpose input GTM input SCU input SENT13D SENT input ARX0A ASCLIN0 input Recommended as Boot loader pin RXDCAN1B CAN node 1 input Used for single pin DAP (SPD) function RXD0A3 ERAY0 input RXD0B3 ERAY0 input EVRWUPA SCU input P14.1 O0 General-purpose output TOUT81 O1 GTM output ATX0 O2 ASCLIN0 output Recommended as Boot loader pin. – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved COUT63 O7 CCU60 output Data Sheet TOC-251 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-60 Port 14 Functions (cont’d) Pin Symbol Ctrl Type Function E13 P14.2 I LP / PU1 / VEXT General-purpose input TIN82 HWCFG2 EVR13 GTM input SCU input Latched at cold power on reset to decide EVR13 activation. P14.2 O0 General-purpose output TOUT82 O1 GTM output ATX2 O2 ASCLIN2 output SLSO21 O3 QSPI2 output – O4 Reserved – O5 Reserved ASCLK2 O6 ASCLIN2 output – O7 Reserved P14.3 B14 I TIN83 ARX2A LP / PU1 / VEXT General-purpose input GTM input ASCLIN2 input REQ10 SCU input HWCFG3_BMI SCU input SDI02 MSC0 input P14.3 O0 General-purpose output TOUT83 O1 GTM output ATX2 O2 ASCLIN2 output SLSO23 O3 QSPI2 output ASLSO1 O4 ASCLIN1 output ASLSO3 O5 ASCLIN3 output – O6 Reserved – O7 Reserved Data Sheet TOC-252 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-60 Port 14 Functions (cont’d) Pin Symbol Ctrl Type Function B15 P14.4 I LP / PU1 / VEXT General-purpose input TIN84 HWCFG6 GTM input SCU input Latched at cold power on reset to decide default pad reset state (PU or HighZ). P14.4 O0 General-purpose output TOUT84 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P14.5 A14 I TIN85 HWCFG1 EVR33 MP+ / PU1 / VEXT General-purpose input GTM input SCU input Latched at cold power on reset to decide EVR33 activation. P14.5 O0 General-purpose output TOUT85 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved TXD0B O6 ERAY0 output TXD1B O7 ERAY1 output P14.6 B13 I TIN86 HWCFG0 DCLDO MP+ / PU1 / VEXT General-purpose input GTM input SCU input If EVR13 active, latched at cold power on reset to decide between LDO and SMPS mode. P14.6 O0 General-purpose output TOUT86 O1 GTM output – O2 Reserved SLSO22 O3 QSPI2 output – O4 Reserved – O5 Reserved TXEN0B O6 ERAY0 output TXEN1B O7 ERAY1 output Data Sheet TOC-253 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-60 Port 14 Functions (cont’d) Pin Symbol Ctrl Type Function D13 P14.7 I LP / PU1 / VEXT General-purpose input TIN87 RXD0B0 RXD1B0 GTM input ERAY0 input ERAY1 input P14.7 O0 General-purpose output TOUT87 O1 GTM output ARTS0 O2 ASCLIN0 output SLSO24 O3 QSPI2 output – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P14.8 A13 I TIN88 ARX1D LP / PU1 / VEXT General-purpose input GTM input ASCLIN1 input RXDCAN2D CAN node 2 input RXD0A0 ERAY0 input RXD1A0 ERAY1 input P14.8 O0 General-purpose output TOUT88 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P14.9 D12 I TIN89 ACTS0A MP+ / PU1 / VEXT General-purpose input GTM input ASCLIN0 input P14.9 O0 General-purpose output TOUT89 O1 GTM output END03 O2 MSC0 output EN01 O3 MSC0 output – O4 Reserved TXEN0B O5 ERAY0 output TXEN0A O6 ERAY0 output TXEN1A O7 ERAY1 output Data Sheet TOC-254 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-60 Port 14 Functions (cont’d) Pin Symbol Ctrl Type Function D11 P14.10 I MP+ / PU1 / VEXT General-purpose input TIN90 GTM input P14.10 O0 General-purpose output TOUT90 O1 GTM output END02 O2 MSC0 output EN00 O3 MSC0 output ATX1 O4 ASCLIN1 output TXDCAN2 O5 CAN node 2 output TXD0A O6 ERAY0 output TXD1A O7 ERAY1 output Table 2-61 Port 15 Functions Pin Symbol Ctrl Type Function B20 P15.0 I LP / PU1 / VEXT General-purpose input TIN71 A18 GTM input P15.0 O0 TOUT71 O1 GTM output ATX1 O2 ASCLIN1 output SLSO013 O3 QSPI0 output – O4 Reserved TXDCAN2 O5 CAN node 2 output ASCLK1 O6 ASCLIN1 output – O7 Reserved P15.1 I TIN72 REQ16 LP / PU1 / VEXT General-purpose output General-purpose input GTM input SCU input ARX1A ASCLIN1 input RXDCAN2A CAN node 2 input SLSI2B QSPI2 input EVRWUPB SCU input P15.1 O0 General-purpose output TOUT72 O1 GTM output ATX1 O2 ASCLIN1 output SLSO25 O3 QSPI2 output – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-255 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-61 Port 15 Functions (cont’d) Pin Symbol Ctrl Type Function C19 P15.2 I MP / PU1 / VEXT General-purpose input TIN73 SLSI2A B17 GTM input QSPI2 input MRST2E QSPI2 input SENT10D SENT input HSIC2INA QSPI2 input P15.2 O0 General-purpose output TOUT73 O1 GTM output ATX0 O2 ASCLIN0 output SLSO20 O3 QSPI2 output – O4 Reserved TXDCAN1 O5 CAN node 1 output ASCLK0 O6 ASCLIN0 output – O7 Reserved P15.3 I TIN74 ARX0B MP / PU1 / VEXT General-purpose input GTM input ASCLIN0 input SCLK2A QSPI2 input RXDCAN1A CAN node 1 input HSIC2INB QSPI2 input P15.3 O0 General-purpose output TOUT74 O1 GTM output ATX0 O2 ASCLIN0 output SCLK2 O3 QSPI2 output END03 O4 MSC0 output EN01 O5 MSC0 output – O6 Reserved – O7 Reserved Data Sheet TOC-256 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-61 Port 15 Functions (cont’d) Pin Symbol Ctrl Type Function A17 P15.4 I MP / PU1 / VEXT General-purpose input TIN75 MRST2A E14 GTM input QSPI2 input REQ0 SCU input SCL0C I2C0 input SENT11D SENT input P15.4 O0 General-purpose output TOUT75 O1 GTM output ATX1 O2 ASCLIN1 output MRST2 O3 QSPI2 output – O4 Reserved – O5 Reserved SCL0 O6 I2C0 output CC62 O7 CCU60 output P15.5 I TIN76 ARX1B MP / PU1 / VEXT General-purpose input GTM input ASCLIN1 input MTSR2A QSPI2 input REQ13 SCU input SDA0C I2C0 input P15.5 O0 General-purpose output TOUT76 O1 GTM output ATX1 O2 ASCLIN1 output MTSR2 O3 QSPI2 output END02 O4 MSC0 output EN00 O5 MSC0 output SDA0 O6 I2C0 output CC61 O7 CCU60 output Data Sheet TOC-257 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-61 Port 15 Functions (cont’d) Pin Symbol Ctrl Type Function A16 P15.6 I MP / PU1 / VEXT General-purpose input TIN77 MTSR2B D15 QSPI2 input P15.6 O0 General-purpose output TOUT77 O1 GTM output ATX3 O2 ASCLIN3 output MTSR2 O3 QSPI2 output SLSO53 O4 QSPI5 output SCLK2 O5 QSPI2 output ASCLK3 O6 ASCLIN3 output CC60 O7 CCU60 output P15.7 I TIN78 ARX3A MP / PU1 / VEXT MRST2B D14 GTM input General-purpose input GTM input ASCLIN3 input QSPI2 input P15.7 O0 General-purpose output TOUT78 O1 GTM output ATX3 O2 ASCLIN3 output MRST2 O3 QSPI2 output – O4 Reserved – O5 Reserved – O6 Reserved COUT60 O7 CCU60 output P15.8 I TIN79 SCLK2B REQ1 MP / PU1 / VEXT General-purpose input GTM input QSPI2 input SCU input P15.8 O0 General-purpose output TOUT79 O1 GTM output – O2 Reserved SCLK2 O3 QSPI2 output – O4 Reserved – O5 Reserved ASCLK3 O6 ASCLIN3 output COUT61 O7 CCU60 output Data Sheet TOC-258 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-62 Port 20 Functions Pin Symbol Ctrl Type Function H20 P20.0 I MP / PU1 / VEXT General-purpose input TIN59 RXDCAN3C G19 GTM input CAN node 3 input RXDCANr1C CAN node 1 input (MultiCANr+) T6EUDA GPT120 input REQ9 SCU input SYSCLK HSCT input TGI0 OCDS input P20.0 O0 General-purpose output TOUT59 O1 GTM output ATX3 O2 ASCLIN3 output ASCLK3 O3 ASCLIN3 output – O4 Reserved SYSCLK O5 HSCT output – O6 Reserved – O7 Reserved TGO0 HWOU T OCDS; ENx P20.1 I TIN60 TGI1 LP / PU1 / VEXT General-purpose input GTM input OCDS input P20.1 O0 General-purpose output TOUT60 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved TGO1 HWOU T OCDS; ENx Data Sheet TOC-259 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-62 Port 20 Functions (cont’d) Pin Symbol Ctrl Type Function H19 P20.2 I LP / PU1 / VEXT General-purpose input This pin is latched at power on reset release to enter test mode. TESTMODE G20 OCDS input P20.2 O0 Output function not available – O1 Output function not available – O2 Output function not available – O3 Output function not available – O4 Output function not available – O5 Output function not available – O6 Output function not available – O7 Output function not available P20.3 I TIN61 T6INA LP / PU1 / VEXT ARX3C F17 General-purpose input GTM input GPT120 input ASCLIN3 input P20.3 O0 General-purpose output TOUT61 O1 GTM output ATX3 O2 ASCLIN3 output SLSO09 O3 QSPI0 output SLSO29 O4 QSPI2 output TXDCAN3 O5 CAN node 3 output TXDCANr1 O6 CAN node 1 output (MultiCANr+) – O7 Reserved P20.6 I TIN62 LP / PU1 / VEXT General-purpose input GTM input P20.6 O0 TOUT62 O1 GTM output ARTS1 O2 ASCLIN1 output SLSO08 O3 QSPI0 output SLSO28 O4 QSPI2 output – O5 Reserved WDT2LCK O6 SCU output – O7 Reserved Data Sheet General-purpose output TOC-260 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-62 Port 20 Functions (cont’d) Pin Symbol Ctrl Type Function F19 P20.7 I LP / PU1 / VEXT General-purpose input TIN63 ACTS1A RXDCAN0B F20 ASCLIN1 input CAN node 0 input P20.7 O0 General-purpose output TOUT63 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved WDT1LCK O6 SCU output COUT63 O7 CCU61 output P20.8 I TIN64 E17 GTM input MP / PU1 / VEXT General-purpose input GTM input P20.8 O0 TOUT64 O1 GTM output ASLSO1 O2 ASCLIN1 output SLSO00 O3 QSPI0 output SLSO10 O4 QSPI1 output TXDCAN0 O5 CAN node 0 output WDT0LCK O6 SCU output CC60 O7 CCU61 output P20.9 I TIN65 ARX1C LP / PU1 / VEXT General-purpose output General-purpose input GTM input ASCLIN1 input RXDCAN3E CAN node 3 input REQ11 SCU input SLSI0B QSPI0 input P20.9 O0 General-purpose output TOUT65 O1 GTM output – O2 Reserved SLSO01 O3 QSPI0 output SLSO11 O4 QSPI1 output – O5 Reserved WDTSLCK O6 SCU output CC61 O7 CCU61 output Data Sheet TOC-261 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-62 Port 20 Functions (cont’d) Pin Symbol Ctrl Type Function E19 P20.10 I MP / PU1 / VEXT General-purpose input TIN66 E20 P20.10 O0 TOUT66 O1 GTM output ATX1 O2 ASCLIN1 output SLSO06 O3 QSPI0 output SLSO27 O4 QSPI2 output TXDCAN3 O5 CAN node 3 output ASCLK1 O6 ASCLIN1 output CC62 O7 CCU61 output P20.11 I TIN67 SCLK0A D19 GTM input MP / PU1 / VEXT General-purpose output General-purpose input GTM input QSPI0 input P20.11 O0 General-purpose output TOUT67 O1 GTM output – O2 Reserved SCLK0 O3 QSPI0 output – O4 Reserved – O5 Reserved – O6 Reserved COUT60 O7 CCU61 output P20.12 I TIN68 MRST0A MP / PU1 / VEXT General-purpose input GTM input QSPI0 input P20.12 O0 General-purpose output TOUT68 O1 GTM output – O2 Reserved MRST0 O3 QSPI0 output MTSR0 O4 QSPI0 output – O5 Reserved – O6 Reserved COUT61 O7 CCU61 output Data Sheet TOC-262 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-62 Port 20 Functions (cont’d) Pin Symbol Ctrl Type Function D20 P20.13 I MP / PU1 / VEXT General-purpose input TIN69 SLSI0A GTM input QSPI0 input P20.13 O0 General-purpose output TOUT69 O1 GTM output – O2 Reserved SLSO02 O3 QSPI0 output SLSO12 O4 QSPI1 output SCLK0 O5 QSPI0 output – O6 Reserved COUT62 O7 CCU61 output P20.14 C20 I TIN70 MTSR0A MP / PU1 / VEXT General-purpose input GTM input QSPI0 input P20.14 O0 General-purpose output TOUT70 O1 GTM output – O2 Reserved MTSR0 O3 QSPI0 output – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Table 2-63 Port 21 Functions Pin Symbol Ctrl Type Function K17 P21.0 I LVDSH_N/ PU1 / VDDP3 General-purpose input TIN51 MRST4DN HOLD GTM input QSPI4 input (LVDS) EBU input P21.0 O0 General-purpose output TOUT51 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved ETHMDC O6 ETH output BAABA0 O7 EBU output (combined for BAA and BA0) HSM1 O HSM output Data Sheet TOC-263 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-63 Port 21 Functions (cont’d) Pin Symbol Ctrl Type Function J17 P21.1 I LVDSH_P/ PU1 / VDDP3 General-purpose input TIN52 ETHMDIOB K19 GTM input ETH input (Not for production purposes) MRST4DP QSPI4 input (LVDS) WAIT EBU input P21.1 O0 General-purpose output TOUT52 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved ETHMDIO O6 ETH output (Not for production purposes) BREQBA1 O7 EBU output (combined for BREQ and BA1) HSM2 O HSM output P21.2 I TIN53 MRST2CN LVDSH_N/ PU1 / VDDP3 General-purpose input GTM input QSPI2 input (LVDS) MRST4CN QSPI4 input (LVDS) ARX3GN ASCLIN3 input (LVDS) EMGSTOPB SCU input RXDN HSCT input (LVDS) P21.2 O0 General-purpose output TOUT53 O1 GTM output ASLSO3 O2 ASCLIN3 output – O3 Reserved – O4 Reserved ETHMDC O5 ETH output SDRAMA8 O6 EBU output – O7 Reserved Data Sheet TOC-264 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-63 Port 21 Functions (cont’d) Pin Symbol Ctrl Type Function J19 P21.3 I LVDSH_P/ PU1 / VDDP3 General-purpose input TIN54 MRST2CP K20 QSPI2 input (LVDS) MRST4CP QSPI4 input (LVDS) ARX3GP ASCLIN3 input (LVDS) RXDP HSCT input (LVDS) P21.3 O0 General-purpose output TOUT54 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved SDRAMA9 O6 EBU output – O7 Reserved ETHMDIOD HWOUT ETH input/output P21.4 I TIN55 J20 GTM input LVDSH_N/ PU1 / VDDP3 General-purpose input GTM input P21.4 O0 TOUT55 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved SDRAMA10 O6 EBU output – O7 Reserved TXDN HSCT HSCT output (LVDS) P21.5 I TIN56 LVDSH_P/ PU1 / VDDP3 General-purpose output General-purpose input GTM input P21.5 O0 TOUT56 O1 GTM output ASCLK3 O2 ASCLIN3 output – O3 Reserved – O4 Reserved – O5 Reserved SDRAMA11 O6 EBU output – O7 Reserved TXDP HSCT HSCT output (LVDS) Data Sheet TOC-265 General-purpose output V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-63 Port 21 Functions (cont’d) Pin Symbol Ctrl Type Function H17 P21.6 I A2 / PU / VDDP3 General-purpose input TIN57 ARX3F H16 GTM input ASCLIN3 input TGI2 OCDS input TDI OCDS (JTAG) input T5EUDA GPT120 input P21.6 O0 General-purpose output TOUT57 O1 GTM output ASLSO3 O2 ASCLIN3 output – O3 Reserved – O4 Reserved SYSCLK O5 HSCT output SDRAMA12 O6 EBU output T3OUT O7 GPT120 output TGO2 HWOUT OCDS; ENx P21.7 I TIN58 DAP2 A2 / PU / VDDP3 General-purpose input GTM input OCDS (3-Pin DAP) input In the 3-Pin DAP mode this pin is used as DAP2. In the 2-PIN DAP mode this pin is used as P21.7 and controlled by the related port control logic TGI3 OCDS input ETHRXERB ETH input T5INA GPT120 input P21.7 O0 General-purpose output TOUT58 O1 GTM output ATX3 O2 ASCLIN3 output ASCLK3 O3 ASCLIN3 output – O4 Reserved – O5 Reserved SDRAMA13 O6 EBU output T6OUT O7 GPT120 output TGO3 HWOUT OCDS; ENx TDO OCDS (JTAG); ENx The JTAG TDO function is overlayed with P21.7 via a double bond. In JTAG mode this pin is used as TDO, after power-on reset it is HighZ. DAP2 OCDS (3-Pin DAP); ENx In the 3-Pin DAP mode this pin is used as DAP2. Data Sheet TOC-266 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-64 Port 22 Functions Pin Symbol Ctrl Type Function P20 P22.0 I LVDSM_N / PU1 / VEXT General-purpose input TIN47 MTSR4B P19 QSPI4 input P22.0 O0 General-purpose output TOUT47 O1 GTM output ATX3N O2 ASCLIN3 output (LVDS) MTSR4 O3 QSPI4 output SCLK4N O4 QSPI4 output (LVDS) FCLN1 O5 MSC1 output (LVDS) FCLND1 O6 MSC1 output (LVDS) – O7 Reserved P22.1 I TIN48 MRST4B R20 GTM input LVDSM_P / PU1 / VEXT General-purpose input GTM input QSPI4 input P22.1 O0 General-purpose output TOUT48 O1 GTM output ATX3P O2 ASCLIN3 output (LVDS) MRST4 O3 QSPI4 output SCLK4P O4 QSPI4 output (LVDS) FCLP1 O5 MSC1 output (LVDS) – O6 Reserved – O7 Reserved P22.2 I TIN49 SLSI4B LVDSM_N / PU1 / VEXT General-purpose input GTM input QSPI4 input P22.2 O0 General-purpose output TOUT49 O1 GTM output – O2 Reserved SLSO43 O3 QSPI4 output MTSR4N O4 QSPI4 output (LVDS) SON1 O5 MSC1 output (LVDS) SOND1 O6 MSC1 output (LVDS) – O7 Reserved Data Sheet TOC-267 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-64 Port 22 Functions (cont’d) Pin Symbol Ctrl Type Function R19 P22.3 I LVDSM_P / PU1 / VEXT General-purpose input TIN50 SCLK4B P16 QSPI4 input P22.3 O0 General-purpose output TOUT50 O1 GTM output – O2 Reserved SCLK4 O3 QSPI4 output MTSR4P O4 QSPI4 output (LVDS) SOP1 O5 MSC1 output (LVDS) – O6 Reserved – O7 Reserved P22.4 I TIN130 P17 GTM input LP / PU1 / VEXT General-purpose input GTM input P22.4 O0 TOUT130 O1 GTM output – O2 Reserved – O3 Reserved SLSO012 O4 QSPI0 output PSITX4 O5 PSI5 output – O6 Reserved – O7 Reserved P22.5 I TIN131 MTSR0C LP / PU1 / VEXT PSIRX4B General-purpose output General-purpose input GTM input QSPI0 input PSI5 input P22.5 O0 General-purpose output TOUT131 O1 GTM output – O2 Reserved – O3 Reserved MTSR0 O4 QSPI0 output – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-268 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-64 Port 22 Functions (cont’d) Pin Symbol Ctrl Type Function N16 P22.6 I LP / PU1 / VEXT General-purpose input TIN132 MRST0C N17 QSPI0 input P22.6 O0 General-purpose output TOUT132 O1 GTM output – O2 Reserved – O3 Reserved MRST0 O4 QSPI0 output – O5 Reserved – O6 Reserved – O7 Reserved P22.7 I TIN133 SCLK0C M16 GTM input LP / PU1 / VEXT General-purpose input GTM input QSPI0 input P22.7 O0 General-purpose output TOUT133 O1 GTM output – O2 Reserved – O3 Reserved SCLK0 O4 QSPI0 output – O5 Reserved – O6 Reserved – O7 Reserved P22.8 I TIN134 SCLK0B LP / PU1 / VEXT General-purpose input GTM input QSPI0 input P22.8 O0 General-purpose output TOUT134 O1 GTM output – O2 Reserved – O3 Reserved SCLK0 O4 QSPI0 output – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-269 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-64 Port 22 Functions (cont’d) Pin Symbol Ctrl Type Function M17 P22.9 I LP / PU1 / VEXT General-purpose input TIN135 MRST0B L16 QSPI0 input P22.9 O0 General-purpose output TOUT135 O1 GTM output – O2 Reserved – O3 Reserved MRST0 O4 QSPI0 output – O5 Reserved – O6 Reserved – O7 Reserved P22.10 I TIN136 MTSR0B L17 GTM input LP / PU1 / VEXT General-purpose input GTM input QSPI0 input P22.10 O0 General-purpose output TOUT136 O1 GTM output – O2 Reserved – O3 Reserved MTSR0 O4 QSPI0 output – O5 Reserved – O6 Reserved – O7 Reserved P22.11 I TIN137 LP / PU1 / VEXT General-purpose input GTM input P22.11 O0 TOUT137 O1 GTM output – O2 Reserved – O3 Reserved SLSO010 O4 QSPI0 output – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-270 General-purpose output V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-65 Port 23 Functions Pin Symbol Ctrl Type Function V20 P23.0 I LP / PU1 / VEXT General-purpose input TIN41 U19 P23.0 O0 TOUT41 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P23.1 I TIN42 SDI10 U20 GTM input MP+ / PU1 / VEXT General-purpose output General-purpose input GTM input MSC1 input P23.1 O0 General-purpose output TOUT42 O1 GTM output ARTS1 O2 ASCLIN1 output SLSO46 O3 QSPI4 output GTMCLK0 O4 GTM output – O5 Reserved EXTCLK0 O6 SCU output – O7 Reserved P23.2 I TIN43 LP / PU1 / VEXT General-purpose input GTM input P23.2 O0 TOUT43 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet General-purpose output TOC-271 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-65 Port 23 Functions (cont’d) Pin Symbol Ctrl Type Function T19 P23.3 I LP / PU1 / VEXT General-purpose input TIN44 INJ10 T20 MSC1 input P23.3 O0 General-purpose output TOUT44 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved P23.4 I TIN45 T17 GTM input MP+ / PU1 / VEXT General-purpose input GTM input P23.4 O0 TOUT45 O1 GTM output – O2 Reserved SLSO45 O3 QSPI4 output END12 O4 MSC1 output EN10 O5 MSC1 output – O6 Reserved – O7 Reserved P23.5 I TIN46 MP+ / PU1 / VEXT General-purpose output General-purpose input GTM input P23.5 O0 TOUT46 O1 GTM output – O2 Reserved SLSO44 O3 QSPI4 output END13 O4 MSC1 output EN11 O5 MSC1 output – O6 Reserved – O7 Reserved Data Sheet General-purpose output TOC-272 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-65 Port 23 Functions (cont’d) Pin Symbol Ctrl Type Function R17 P23.6 I LP / PU1 / VEXT General-purpose input TIN138 R16 GTM input P23.6 O0 TOUT138 O1 GTM output – O2 Reserved – O3 Reserved SLSO011 O4 QSPI0 output – O5 Reserved – O6 Reserved – O7 Reserved P23.7 I TIN139 LP / PU1 / VEXT General-purpose output General-purpose input GTM input P23.7 O0 General-purpose output TOUT139 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Table 2-66 Port 32 Functions Pin Symbol Ctrl Type Function Y17 P32.0 I LP / PX/ VEXT General-purpose input TIN36 FDEST VGATE1N GTM input PMU input SMPS mode: analog output. External Pass Device gate control for EVR13 P32.0 O0 General-purpose output TOUT36 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved Data Sheet TOC-273 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-66 Port 32 Functions (cont’d) Pin Symbol Ctrl Type Function Y18 P32.2 I LP / PU1 / VEXT General-purpose input TIN38 ARX3D GTM input ASCLIN3 input RXDCAN3B CAN node 3 input RXDCANr1D CAN node 1 input (MultiCANr+) P32.2 O0 General-purpose output TOUT38 O1 GTM output ATX3 O2 ASCLIN3 output – O3 Reserved – O4 Reserved – O5 Reserved DCDCSYNC O6 SCU output – O7 Reserved P32.3 Y19 I TIN39 LP / PU1 / VEXT General-purpose input GTM input P32.3 O0 TOUT39 O1 GTM output ATX3 O2 ASCLIN3 output – O3 Reserved ASCLK3 O4 ASCLIN3 output TXDCAN3 O5 CAN node 3 output TXDCANr1 O6 CAN node 1 output (MultiCANr+) – O7 Reserved P32.4 W18 I TIN40 ACTS1B SDI12 MP+ / PU1 / VEXT General-purpose output General-purpose input GTM input ASCLIN1 input MSC1 input P32.4 O0 General-purpose output TOUT40 O1 GTM output – O2 Reserved END12 O3 MSC1 output GTMCLK1 O4 GTM output EN10 O5 MSC1 output EXTCLK1 O6 SCU output COUT63 O7 CCU60 output Data Sheet TOC-274 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-66 Port 32 Functions (cont’d) Pin Symbol Ctrl Type Function T15 P32.5 I LP / PU1 / VEXT General-purpose input TIN140 GTM input P32.5 O0 TOUT140 O1 GTM output ATX2 O2 ASCLIN2 output – O3 Reserved – O4 Reserved – O5 Reserved TXDCAN2 O6 CAN node 2 output – O7 Reserved P32.6 U15 I TGI4 TIN141 LP / PU1 / VEXT General-purpose output General-purpose input OCDS input GTM input RXDCAN2C CAN node 2 input ARX2F ASCLIN2 input P32.6 O0 General-purpose output TOUT141 O1 GTM output – O2 Reserved – O3 Reserved SLSO212 O4 QSPI2 output – O5 Reserved – O6 Reserved – O7 Reserved TGO4 HWOU T OCDS; ENx P32.7 U16 I TIN142 TGI5 LP / PU1 / VEXT General-purpose input GTM input OCDS input P32.7 O0 General-purpose output TOUT142 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved – O7 Reserved TGO5 HWOU T OCDS; ENx Data Sheet TOC-275 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-67 Port 33 Functions Pin Symbol Ctrl Type Function W10 P33.0 I LP / PU1 / VEXT General-purpose input TIN22 DSITR0E GTM input DSADC channel 0 input E P33.0 O0 General-purpose output TOUT22 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved VADCG2BFL0 O6 VADC output – O7 Reserved P33.1 Y10 I TIN23 PSIRX0C LP / PU1 / VEXT General-purpose input GTM input PSI5 input SENT9C SENT input DSCIN2B DSADC channel 2 input B DSITR1E DSADC channel 1 input E P33.1 O0 General-purpose output TOUT23 O1 GTM output ASLSO3 O2 ASCLIN3 output SCLK2 O3 QSPI2 output DSCOUT2 O4 DSADC channel 2 output VADCEMUX02 O5 VADC output VADCG2BFL1 O6 VADC output – O7 Reserved P33.2 W11 I TIN24 SENT8C LP / PU1 / VEXT General-purpose input GTM input SENT input DSDIN2B DSADC channel 2 input B DSITR2E DSADC channel 2 input E P33.2 O0 General-purpose output TOUT24 O1 GTM output ASCLK3 O2 ASCLIN3 output SLSO210 O3 QSPI2 output PSITX0 O4 PSI5 output VADCEMUX01 O5 VADC output VADCG2BFL2 O6 VADC output – O7 Reserved Data Sheet TOC-276 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-67 Port 33 Functions (cont’d) Pin Symbol Ctrl Type Function Y11 P33.3 I LP / PU1 / VEXT General-purpose input TIN25 PSIRX1C GTM input PSI5 input SENT7C SENT input DSCIN1B DSADC channel 1 input B P33.3 O0 General-purpose output TOUT25 O1 GTM output – O2 Reserved – O3 Reserved DSCOUT1 O4 DSADC channel 1 output VADCEMUX00 O5 VADC output VADCG2BFL3 O6 VADC output – O7 Reserved P33.4 W12 I TIN26 SENT6C LP / PU1 / VEXT General-purpose input GTM input SENT input CTRAPC CCU61 input DSDIN1B DSADC channel 1 input DSITR0F DSADC channel 0 input F P33.4 O0 General-purpose output TOUT26 O1 GTM output ARTS2 O2 ASCLIN2 output SLSO212 O3 QSPI2 output PSITX1 O4 PSI5 output VADCEMUX12 O5 VADC output VADCG0BFL0 O6 VADC output – O7 Reserved Data Sheet TOC-277 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-67 Port 33 Functions (cont’d) Pin Symbol Ctrl Type Function Y12 P33.5 I LP / PU1 / VEXT General-purpose input TIN27 ACTS2B GTM input ASCLIN2 input PSIRX2C PSI5 input PSISRXC PSI5-S input SENT5C SENT input CCPOS2C CCU61 input T4EUDB GPT120 input DSCIN0B DSADC channel 0 input B DSITR1F DSADC channel 1 input F P33.5 O0 General-purpose output TOUT27 O1 GTM output SLSO07 O2 QSPI0 output SLSO17 O3 QSPI1 output DSCOUT0 O4 DSADC channel 0 output VADCEMUX11 O5 VADC output VADCG0BFL1 O6 VADC output – O7 Reserved P33.6 W13 I TIN28 SENT4C LP / PU1 / VEXT General-purpose input GTM input SENT input CCPOS1C CCU61 input T2EUDB GPT120 input DSDIN0B DSADC channel 0 input B DSITR2F DSADC channel 2 input F P33.6 O0 General-purpose output TOUT28 O1 GTM output ASLSO2 O2 ASCLIN2 output SLSO211 O3 QSPI2 output PSITX2 O4 PSI5 output VADCEMUX10 O5 VADC output VADCG1BFL0 O6 VADC output PSISTX O7 PSI5-S output Data Sheet TOC-278 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-67 Port 33 Functions (cont’d) Pin Symbol Ctrl Type Function Y13 P33.7 I LP / PU1 / VEXT General-purpose input TIN29 RXDCAN0E GTM input CAN node 0 input REQ8 SCU input CCPOS0C CCU61 input T2INB GPT120 input P33.7 O0 General-purpose output TOUT29 O1 GTM output ASCLK2 O2 ASCLIN2 output SLSO47 O3 QSPI4 output – O4 Reserved – O5 Reserved VADCG1BFL1 O6 VADC output – O7 Reserved P33.8 W14 I TIN30 ARX2E MP / HighZ / VEXT EMGSTOPA General-purpose input GTM input ASCLIN2 input SCU input P33.8 O0 General-purpose output TOUT30 O1 GTM output ATX2 O2 ASCLIN2 output SLSO42 O3 QSPI4 output – O4 Reserved TXDCAN0 O5 CAN node 0 output – O6 Reserved COUT62 O7 CCU61 output SMUFSP HWOU T SMU P33.9 Y14 I TIN31 HSIC3INA LP / PU1 / VEXT General-purpose input GTM input QSPI3 input P33.9 O0 General-purpose output TOUT31 O1 GTM output ATX2 O2 ASCLIN2 output SLSO41 O3 QSPI4 output ASCLK2 O4 ASCLIN2 output – O5 Reserved – O6 Reserved CC62 O7 CCU61 output Data Sheet TOC-279 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-67 Port 33 Functions (cont’d) Pin Symbol Ctrl Type Function W15 P33.10 I MP / PU1 / VEXT General-purpose input TIN32 SLSI4A HSIC3INB GTM input QSPI4 input QSPI3 input P33.10 O0 General-purpose output TOUT32 O1 GTM output SLSO16 O2 QSPI1 output SLSO40 O3 QSPI4 output ASLSO1 O4 ASCLIN1 output PSISCLK O5 PSI5-S output – O6 Reserved COUT61 O7 CCU61 output P33.11 Y15 I TIN33 SCLK4A MP / PU1 / VEXT General-purpose input GTM input QSPI4 input P33.11 O0 General-purpose output TOUT33 O1 GTM output ASCLK1 O2 ASCLIN1 output SCLK4 O3 QSPI4 output – O4 Reserved – O5 Reserved DSCGPWMN O6 DSADC channel output CC61 O7 CCU61 output P33.12 W16 I TIN34 MTSR4A MP / PU1 / VEXT General-purpose input GTM input QSPI4 input P33.12 O0 General-purpose output TOUT34 O1 GTM output ATX1 O2 ASCLIN1 output MTSR4 O3 QSPI4 output ASCLK1 O4 ASCLIN1 output – O5 Reserved DSCGPWMP O6 DSADC output COUT60 O7 CCU61 output Data Sheet TOC-280 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-67 Port 33 Functions (cont’d) Pin Symbol Ctrl Type Function Y16 P33.13 I MP / PU1 / VEXT General-purpose input TIN35 ARX1F GTM input ASCLIN1 input MRST4A QSPI4 input DSSGNB DSADC channel input B INJ11 MSC1 input P33.13 O0 General-purpose output TOUT35 O1 GTM output ATX1 O2 ASCLIN1 output MRST4 O3 QSPI4 output SLSO26 O4 QSPI2 output – O5 Reserved DCDCSYNC O6 SCU output CC60 O7 CCU61 output P33.14 T14 I TIN143 TGI6 SCLK2D LP / PU1 / VEXT General-purpose input GTM input OCDS input QSPI2 input P33.14 O0 General-purpose output TOUT143 O1 GTM output – O2 Reserved SCLK2 O3 QSPI2 output – O4 Reserved – O5 Reserved – O6 Reserved CC62 O7 CCU60 output TGO6 HWOU T OCDS; ENx Data Sheet TOC-281 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-67 Port 33 Functions (cont’d) Pin Symbol Ctrl Type Function U14 P33.15 I LP / PU1 / VEXT General-purpose input TIN144 TGI7 GTM input OCDS input P33.15 O0 General-purpose output TOUT144 O1 GTM output – O2 Reserved SLSO211 O3 QSPI2 output – O4 Reserved – O5 Reserved – O6 Reserved COUT62 O7 CCU60 output TGO7 HWOU T OCDS; ENx Table 2-68 Port 34 Functions Pin Symbol Ctrl Type Function U11 P34.1 I LP / PU1 / VEXT General-purpose input TIN146 T12 GTM input P34.1 O0 TOUT146 O1 GTM output ATX0 O2 ASCLIN0 output – O3 Reserved TXDCAN0 O4 CAN node 0 output TXDCANr0 O5 CAN node 0 output (MultiCANr+) – O6 Reserved COUT63 O7 CCU60 output P34.2 I TIN147 ARX0D LP / PU1 / VEXT General-purpose output General-purpose input GTM input ASCLIN0 input RXDCAN0G CAN node 0 input RXDCANr0C CAN node 0 input (MultiCANr+) P34.2 O0 General-purpose output TOUT147 O1 GTM output – O2 Reserved – O3 Reserved – O4 Reserved – O5 Reserved – O6 Reserved CC60 O7 CCU60 output Data Sheet TOC-282 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-68 Port 34 Functions (cont’d) Pin Symbol Ctrl Type Function U12 P34.3 I LP / PU1 / VEXT General-purpose input TIN148 T13 P34.3 O0 TOUT148 O1 GTM output – O2 Reserved – O3 Reserved SLSO210 O4 QSPI2 output – O5 Reserved – O6 Reserved COUT60 O7 CCU60 output P34.4 I TIN149 MRST2D U13 GTM input LP / PU1 / VEXT General-purpose output General-purpose input GTM input QSPI2 input P34.4 O0 General-purpose output TOUT149 O1 GTM output – O2 Reserved – O3 Reserved MRST2 O4 QSPI2 output – O5 Reserved – O6 Reserved CC61 O7 CCU60 output P34.5 I TIN150 MTSR2D LP / PU1 / VEXT General-purpose input GTM input QSPI2 input P34.5 O0 General-purpose output TOUT150 O1 GTM output – O2 Reserved – O3 Reserved MTSR2 O4 QSPI2 output – O5 Reserved – O6 Reserved COUT61 O7 CCU60 output Data Sheet TOC-283 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-69 Port 40 Functions Pin Symbol Ctrl Type Function W2 P40.0 I S/ HighZ / VDDM General-purpose input VADCG3.0 DS2PB VADC analog input channel 0 of group 3 DSADC: positive analog input of channel 2, pin B CCPOS0D CCU60 input SENT0A SENT input P40.1 W1 I VADCG3.1 S/ HighZ / VDDM General-purpose inpu.t VADC analog input channel 1 of group 3 (with pull down diagnostics) DS2NB DSADC: negative analog input channel 2, pin B CCPOS1B CCU60 input SENT1A SENT input P40.2 V2 I VADCG3.2 S/ HighZ / VDDM General-purpose inpu.t VADC analog input channel 2 of group 3 (with pull down diagnostics) CCPOS1D CCU60 input SENT2A SENT input P40.3 V1 I VADCG3.3 S/ HighZ / VDDM General-purpose input VADC analog input channel 3 of group 3 (with pull down diagnostics) CCPOS2B CCU60 input SENT3A SENT input P40.4 P4 I VADCG4.0 CCPOS2D S/ HighZ / VDDM SENT4A P40.5 R1 I CCPOS0D S/ HighZ / VDDM SENT5A P40.6 VADCG4.4 DS3PA VADC analog input channel 0 of group 4 CCU60 input SENT input VADCG4.1 N4 General-purpose input General-purpose input VADC analog input channel 1 of group 4 CCU61 input SENT input I S/ HighZ / VDDM General-purpose input VADC analog input channel 4 of group 4 DSADC: positive analog input of channel 3, pin A CCPOS1B CCU61 input SENT6A SENT input Data Sheet TOC-284 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-69 Port 40 Functions (cont’d) Pin Symbol Ctrl Type Function P2 P40.7 I S/ HighZ / VDDM General-purpose input VADCG4.5 DS3NA VADC analog input channel 5 of group 4 DSADC: negative analog input channel 3, pin A CCPOS1D CCU61 input SENT7A SENT input P40.8 N5 I VADCG4.6 DS3PB S/ HighZ / VDDM General-purpose input VADC analog input channel 6 of group 4 DSADC: positive analog input of channel 3, pin B CCPOS2B CCU61 input SENT8A SENT input P40.9 P1 I VADCG4.7 DS3NB S/ HighZ / VDDM General-purpose input VADC analog input channel 7 of group 4 DSADC: negative analog input channel 3, pin B CCPOS2D CCU61 input SENT9A SENT input Table 2-70 Analog Inputs Pin Symbol Ctrl Type T10 AN0 I D / HighZ / Analog input 0 VDDM VADC analog input channel 0 of group 0 VADCG0.0 DS1PA AN1 U10 DSADC: positive analog input of channel 1, pin A I VADCG0.1 DS1NA AN2 W9 I DS0PA AN3 I DS0NA AN4 AN5 I D / HighZ / Analog input 4 VDDM VADC analog input channel 4 of group 0 I D / HighZ / Analog input 5 VDDM VADC analog input channel 5 of group 0 I D / HighZ / Analog input 6 VDDM VADC analog input channel 6 of group 0 I D / HighZ / Analog input 7 VDDM VADC analog input channel 7 of group 0 VADCG0.5 AN6 T8 VADCG0.6 AN7 U8 VADCG0.7 Data Sheet D / HighZ / Analog input 3 VDDM VADC analog input channel 3 of group 0 DSADC: negative analog input channel 0, pin A VADCG0.4 Y9 D / HighZ / Analog input 2 VDDM VADC analog input channel 2 of group 0 DSADC: positive analog input of channel 0, pin A VADCG0.3 T9 D / HighZ / Analog input 1 VDDM VADC analog input channel 1 of group 0 DSADC: negative analog input channel 1, pin A VADCG0.2 U9 Function TOC-285 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-70 Analog Inputs (cont’d) Pin Symbol Ctrl Type W8 AN8 I D / HighZ / Analog input 8 VDDM VADC analog input channel 0 of group 1 I D / HighZ / Analog input 9 VDDM VADC analog input channel 1 of group 1 I D / HighZ / Analog input 10 VDDM VADC analog input channel 2 of group 1 I D / HighZ / Analog input 11 VDDM VADC analog input channel 3 of group 1 (with pull down diagnostics) I D / HighZ / Analog input 12 VDDM VADC analog input channel 4 of group 1 I D / HighZ / Analog input 13 VDDM VADC analog input channel 5 of group 1 I D / HighZ / Analog input 14 VDDM VADC analog input channel 6 of group 1 I D / HighZ / Analog input 15 VDDM VADC analog input channel 7 of group 1 I D / HighZ / Analog input 16 VDDM VADC analog input channel 0 of group 2 I D / HighZ / Analog input 17 VDDM VADC analog input channel 1 of group 2 I D / HighZ / Analog input 18 VDDM VADC analog input channel 2 of group 2 I D / HighZ / Analog input 19 VDDM VADC analog input channel 3 of group 2 (with pull down diagnostics) I D / HighZ / Analog input 20 VDDM VADC analog input channel 4 of group 2 VADCG1.0 AN9 U7 VADCG1.1 AN10 Y8 VADCG1.2 AN11 W7 VADCG1.3 AN12 T7 VADCG1.4 AN13 W6 VADCG1.5 AN14 U6 VADCG1.6 AN15 T6 VADCG1.7 AN16 W5 VADCG2.0 AN17 U5 VADCG2.1 AN18 W4 VADCG2.2 AN19 W3 VADCG2.3 AN20 Y3 VADCG2.4 DS2PA AN21 Y2 DSADC: positive analog input of channel 2, pin A I VADCG2.5 DS2NA AN22 T5 AN23 VADCG2.7 Data Sheet D / HighZ / Analog input 21 VDDM VADC analog input channel 5 of group 2 DSADC: negative analog input channel 2, pin A I D / HighZ / Analog input 22 VDDM VADC analog input channel 6 of group 2 I D / HighZ / Analog input 23 VDDM VADC analog input channel 7 of group 2 VADCG2.6 R5 Function TOC-286 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-70 Analog Inputs (cont’d) Pin Symbol Ctrl Type Function W2 AN24 I S/ HighZ / VDDM Analog input 24 VADCG3.0 DS2PB SENT0A AN25 W1 VADC analog input channel 0 of group 3 DSADC: positive analog input of channel 2, pin B SENT input channel 0, pin A I VADCG3.1 S/ HighZ / VDDM Analog input 24 VADC analog input channel 1 of group 3 (with pull down diagnostics) DS2NB DSADC: negative analog input channel 2, pin B SENT1A SENT input channel 1, pin A AN26 V2 I VADCG3.2 S/ HighZ / VDDM SENT2A AN27 V1 I S/ HighZ / VDDM SENT3A AN28 AN29 AN30 D / HighZ / Analog input 28 VDDM VADC analog input channel 4 of group 3 (with pull down diagnostics) I D / HighZ / Analog input 29 VDDM VADC analog input channel 5 of group 3 (with pull down diagnostics) I D / HighZ / Analog input 30 VDDM VADC analog input channel 6 of group 3 I D / HighZ / Analog input 31 VDDM VADC analog input channel 7 of group 3 I S/ HighZ / VDDM VADCG3.6 AN31 R4 VADCG3.7 AN32 P4 VADCG4.0 SENT4A AN33 R1 I VADCG4.1 SENT5A AN34 P5 AN35 VADCG4.3 Data Sheet S/ HighZ / VDDM Analog input 32 VADC analog input channel 0 of group 4 SENT input channel 4, pin A Analog input 33 VADC analog input channel 1 of group 4 SENT input channel 5, pin A I D / HighZ / Analog input 34 VDDM VADC analog input channel 2 of group 4 I D / HighZ / Analog input 35 VDDM VADC analog input channel 3 of group 4 (with pull down diagnostics) VADCG4.2 R2 VADC analog input channel 3 of group 3 (with pull down diagnostics) I VADCG3.5 T4 Analog input 27 SENT input channel 3, pin A VADCG3.4 U1 VADC analog input channel 2 of group 3 (with pull down diagnostics) SENT input channel 2, pin A VADCG3.3 U2 Analog input 26 TOC-287 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-70 Analog Inputs (cont’d) Pin Symbol Ctrl Type Function N4 AN36 I S/ HighZ / VDDM Analog input 34 VADCG4.4 DS3PA SENT6A AN37 P2 I DS3NA S/ HighZ / VDDM SENT7A AN38 I DS3PB S/ HighZ / VDDM SENT8A AN39 I DS3NB SENT9A AN40 AN41 AN42 AN43 AN44 D / HighZ / Analog input 43 VDDM VADC analog input channel 3 of group 5 (with pull down diagnostics) I D / HighZ / Analog input 44 VDDM VADC analog input channel 4 of group 5 DSADC: positive analog input of channel 3, pin C I I DS3PD AN47 VADCG5.7 DS3ND Data Sheet D / HighZ / Analog input 45 VDDM VADC analog input channel 5 of group 5 DSADC: negative analog input channel 3, pin C VADCG5.6 M2 DSADC: negative analog input channel 3, pin B I DS3NC AN46 VADC analog input channel 7 of group 4 D / HighZ / Analog input 42 VDDM VADC analog input channel 2 of group 5 VADCG5.5 M1 Analog input 39 I DS3PC AN45 S/ HighZ / VDDM D / HighZ / Analog input 41 VDDM VADC analog input channel 1 of group 5 VADCG5.4 N2 DSADC: positive analog input of channel 3, pin B I VADCG5.3 N1 VADC analog input channel 6 of group 4 D / HighZ / Analog input 40 VDDM VADC analog input channel 0 of group 5 VADCG5.2 L4 Analog input 38 I VADCG5.1 L5 DSADC: negative analog input channel 3, pin A SENT input channel 9, pin A VADCG5.0 M4 VADC analog input channel 5 of group 4 SENT input channel 8, pin A VADCG4.7 M5 Analog input 37 SENT input channel 7, pin A VADCG4.6 P1 DSADC: positive analog input of channel 3, pin A SENT input channel 6, pin A VADCG4.5 N5 VADC analog input channel 4 of group 4 D / HighZ / Analog input 46 VDDM VADC analog input channel 6 of group 5 DSADC: positive analog input of channel 3, pin D I D / HighZ / Analog input 47 VDDM VADC analog input channel 7 of group 5 DSADC: negative analog input channel 3, pin D TOC-288 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-71 System I/O Pin Symbol Ctrl Type Function G17 PORST I PORST / PD / VEXT Power On Reset Input Additional strong PD in case of power fail. F16 ESR0 I/O MP / OD / VEXT External System Request Reset 0 Default configuration during and after reset is opendrain driver. The driver drives low during power-on reset. This is valid additionally after deactivation of PORST until the internal reset phase has finished. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. EVRWUP ESR1 G16 EVRWUP I I/O EVR Wakeup Pin External System Request Reset 1 Default NMI function. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description. MP / PU1 / VEXT I EVR Wakeup Pin W17 VGATE1P O VGATE1P / -/ VEXT External Pass Device gate control for EVR13 K16 TMS I A2 / PD / VDDP3 JTAG Module State Machine Control Input DAP1 I/O Device Access Port Line 1 L19 TRST I A2 / PD / VDDP3 JTAG Module Reset/Enable Input J16 TCK I JTAG Module Clock Input DAP0 I A2 / PD / VDDP3 Device Access Port Line 0 M20 XTAL1 I XTAL1 / -/ VDDP3 Main Oscillator/PLL/Clock Generator Input M19 XTAL2 O XTAL2 / -/ VDDP3 Main Oscillator/PLL/Clock Generator Output Table 2-72 Supply Pin Symbol Ctrl Type Function Y6 VAREF1 I Vx Positive Analog Reference Voltage 1 Y7 VAGND1 I Vx Negative Analog Reference Voltage 1 Data Sheet TOC-289 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-72 Supply (cont’d) Pin Symbol Ctrl Type Function T1 VAREF2 I Vx Positive Analog Reference Voltage 2 T2 VAGND2 I Vx Negative Analog Reference Voltage 2 Y5 VDDM I Vx ADC Analog Power Supply (3.3V / 5V) G8, H7 VDD / VDDSB I Vx Emulation Device: Emulation SRAM Standby Power Supply (1.3V) (Emulation Device only). Production Device: VDD (1.3V). P8, P13, N7, N14, H14, G13 VDD I Vx Digital Core Power Supply (1.3V) N19 VDD I Vx Digital Core Power Supply (1.3V). The supply pin inturn supplies the main XTAL Oscillator/PLL (1.3V) . A higher decoupling capacitor is therefore recommended to the VSS pin for better noise immunity. A2, B3, V19, W20 VEXT I Vx External Power Supply (5V / 3.3V) B18, A19 VDDP3 I Vx Digital Power Supply for Flash (3.3V). Can be also used as external 3.3V Power Supply for VFLEX. N20 VDDP3 I Vx Digital Power Supply for Oscillator, LVDSH and A2 pads (3.3V). The supply pin inturn supplies the main XTAL Oscillator/PLL (3.3V) . A higher decoupling capacitor is therefore recommended to the VSS pin for better noise immunity. E15, D16 VDDFL3 I Vx Flash Power Supply (3.3V) D5 VFLEX I Vx Digital Power Supply for Flex Port Pads (5V / 3.3V) Y4 VSSM I Vx Analog Ground for VDDM T11 VEVRSB I Vx Standby Power Supply (3.3V/5V) for the Standby SRAM (CPU0.DSPR). If Standby mode is not used: To be handled like VEXT (3.3V/5V). B2, D4, E5, T16, U17, W19, VSS Y20, E16, D17, B19, A20, L20 I Vx Digital Ground (outer balls) VSS I Vx Digital Ground (center balls) P9, P12, N9, N10, N11, N12 Data Sheet TOC-290 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-72 Supply (cont’d) Pin Symbol Ctrl Type Function M7, M8, M10, M11, M13, M14 VSS I Vx Digital Ground (center balls) L8, L9, L10, L11, L12, L13 VSS I Vx Digital Ground (center balls) K8, K9, K10, K11, K12, K13 VSS I Vx Digital Ground (center balls) J7, J8, J10, J11, J13, J14 VSS I Vx Digital Ground (center balls) H9, H10, H11, H12, G9, G10, G11, G12 VSS I Vx Digital Ground (center balls) P10 VSS I Vx Digital Ground (center balls) This ball is used in the Emulation Device as AGBT TX0N P11 VSS I Vx Digital Ground (center balls) This ball is used in the Emulation Device as AGBT TX0P L7 VSS I Vx Digital Ground (center balls) This ball is used in the Emulation Device as AGBT CLKN K7 VSS I Vx Digital Ground (center balls) This ball is used in the Emulation Device as AGBT CLKP L14 VSS I Vx Digital Ground (center balls) This ball is used in the Emulation Device as AGBT ERR K14 NC / VDDPSB I NCVDD Emulation Device: Power Supply (3.3V) PSB for DAP/JTAG pad group. Can be connected to VDDP or can be left unsupplied (see document ´AurixED´ / Aurix Emulation Devices specification. Production Device: This pin is not connected on package level. It can be connected on PCB level to VDDP or Ground or can be left unsupplied. A1, Y1, U4 Data Sheet NC I TOC-291 NC1 Not Connected. These pins are not connected on package level and will not be used for future extensions. V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Legend: Column “Ctrl.”: I = Input (for GPIO port Lines with IOCR bit field Selection PCx = 0XXXB) O = Output O0 = Output with IOCR bit field selection PCx = 1X000B O1 = Output with IOCR bit field selection PCx = 1X001B (ALT1) O2 = Output with IOCR bit field selection PCx = 1X010B (ALT2) O3 = Output with IOCR bit field selection PCx = 1X011B (ALT3) O4 = Output with IOCR bit field selection PCx = 1X100B (ALT4) O5 = Output with IOCR bit field selection PCx = 1X101B (ALT5) O6 = Output with IOCR bit field selection PCx = 1X110B (ALT6) O7 = Output with IOCR bit field selection PCx = 1X111B (ALT7) Column “Type”: LP = Pad class LP (5V/3.3V, Class LP parameters for digital input / output and class D parameters for analog input function) MP = Pad class MP (5V/3.3V) MP+ = Pad class MP+ (5V/3.3V) MPR = Pad class MPR (5V/3.3V) A2 = Pad class A2 (3.3V) LVDSM = Pad class LVDSM (5V/3.3V) LVDSH = Pad class LVDSH (3.3V) S = Pad class S (Class S parameters for digital input and class D parameters for analog input function) D = Pad class D (VADC / DSADC) PU = with pull-up device connected during reset (PORST = 0) PU1 = with pull-up device connected during reset (PORST = 0)1) 2) 3) PD = with pull-down device connected during reset (PORST = 0) PD1 = with pull-down device connected during reset (PORST = 0)1) 2) 3) PX = Behavior depends on usage: PD in EVR13 SMPS Mode and PU1 in GPIO Mode OD = open drain during reset (PORST = 0) HighZ = tri-state during reset (PORST = 0) PORST = PORST input pad XTAL1 = XTAL1 input pad XTAL2 = XTAL2 input pad VGATE1P = VGATE1P VGATE3P = VGATE3P Vx = Supply NC = These pins are reserved for future extensions and shall not be connected externally NC1 = These pins are not connected on package level and will not be used for future extensions NCVDDPSB = This pin has a different functionality in an Production Device and an Emulation Device. For details pls. see Pin/Ball description of this pin. NCVDDSB = This pin has a different functionality in an Production Device and an Emulation Device. For details pls. see Pin/Ball description of this pin. 1) The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG[6] (P14.4). HWCFG[6] has a weak internal pull-up active at start-up if the pin is left unconnected.See also User´s Manual, “Introduction Chapter”, “General Purpose I/O Ports and Peripheral I/O Lines”, Figure: “Default state of port pins during and after reset”. 2) If HWCFG[6] is left unconnected or is externally pulled high, weak internal pull-ups (PU1) / pull-downs (PD1) are active during and after reset. 3) If HWCFG[6] is connected to ground, the PD1 / PU1 pins are predominantly in HighZ during and after reset. Data Sheet TOC-292 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: 2.3.2 Emergency Stop Function The Emergency Stop function can be used to force GPIOs (General Purpose Inputs/Outputs) via an external input signal (EMGSTOPA or EMGSTOPB) into a defined state: • Input state and • PU or High-Z depending on HWCFG[6] level latched during Porst active Control of the Emergency Stop function: • The Emergency Stop function can be enabled/disabled in the SCU (see chapter “SCU”, “Emergency Stop Control”) • The Emergency Stop input signal, EMGSTOPA (P33.8) / EMGSTOPB (P21.2) , can selected in the SCU (see chapter “SCU”, “Emergency Stop Control”) • On port level, each GPIO can be enabled/disabled for the Emergency Stop function via the Px_ESR (Port x Emergency Stop) registers in the port control logic (see chapter “General Purpose I/O Ports and Peripheral I/O Lines”, “Emergency Stop Register”). The Emergency Stop function is available for all GPIO Ports with the following exceptions: • Not available for P20.2 (General Purpose Input/GPI only, overlayed with Testmode) • Not available for P40.x (analoge input ANx overlayed with GPI) • Not available for P32.0 EVR13 SMPS mode. • Not available for dedicated I/O without General Purpose Output function (e.g ESRx, TMS, TCK) The Emergency Stop function can be overruled on the following GPIO Ports: • P00.x and P02.x: Emergency Stop can be overruled by the 8-Bit Standby Controller (SBR), if implemented. Overruling can be disabled via the control registers P00_SCR / P02_SCR (see chapter “General Purpose I/O Ports and Peripheral I/O Lines”, P00 / P01) • P00.x: Emergency Stop can be overruled by the VADC. Overruling can be disabled via the control register P00_SCR (see chapter “General Purpose I/O Ports and Peripheral I/O Lines”, P00) • P14.0 and P14.1: Emergency Stop can be overruled in the DXCPL mode (DAP over can physical layer mode). No Overruling in the DXCM (Debug over can message) mode • P21.6: Emergency Stop can be overruled in JTAG mode if this pin is used as TDI • P21.7: Emergency Stop can be overruled in JTAG or Three Pin DAP mode • P20.0: Emergency Stop can be overruled in JTAG mode if this GPIO is used as TDI • P33.8: Emergency Stop can be overruled if this pin is used as safety output pin (SMUFSP) 2.3.3 Pull-Up/Pull-Down Reset Behavior of the Pins Table 2-73 List of Pull-Up/Pull-Down Reset Behavior of the Pins Pins PORST = 0 all GPIOs Pull-up if HWCFG[6] = 1 or High-Z if HWCFG[6] = 0 TDI, TESTMODE Pull-up 1) PORST Pull-down with IPORST relevant TRST, TCK, TMS Pull-down ESR0 The open-drain driver is used to drive low.2) Data Sheet TOC-293 PORST = 1 Pull-down with IPDLI relevant Pull-up3) V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC297x Pin Definition and Functions: Table 2-73 List of Pull-Up/Pull-Down Reset Behavior of the Pins Pins PORST = 0 ESR1 Pull-up3) TDO Pull-up 1) 2) 3) 4) PORST = 1 High-Z/Pull-up4) Pull-down with IPORST relevant is always activated when a primary supply monitor detects a violation. Valid additionally after deactivation of PORST until the internal reset phase has finished. See the SCU chapter for details. See the SCU_IOCR register description. Depends on JTAG/DAP selection with TRST. In case of leakage test (PORST = 0 and TESTMODE = 0), the pull-down of the TRST pin is switched off. In case of an user application (TESTMODE = 1), the pull-down of the TRST is always switched on. Data Sheet TOC-294 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC29x Bare Die Pad Definition 2.4 TC29x Bare Die Pad Definition The TC290 / TC297 / TC298 / TC299 BC-Step Bare Die Logic Symbol is shown in Figure 2-4. Table 2-74 describes the pads of the TC290 / TC297 / TC298 / TC299 bare die. It describes also the mapping of VADC / DS-ADC channels to the analog inputs (ANx) and the mapping of Port functions to the pads. The detailed description of the port functions (Px.y) can be found in the User’s Manual chapter “General Purpose I/O Ports and Peripheral I/O LInes (Ports)“. Pad 366 Pad 234 Pad 233 Pad 367 Y 0.0 X Pad 480 Pad 102 Pad 1 Pad 101 Figure 2-4 TC290 / TC297 / TC298 / TC299 Logic Symbol for the Bare Die. Table 2-74 TC29x Bare Die Pad List Number Pad Name Pad Type X Y Comment 1 VEXT Vx -4328000 -4295000 Must be bonded to VEXT 2 P15.10 LP / PU1 / VEXT -4123000 -4186500 GPIO 3 P15.2 MP / PU1 / VEXT -4193000 -4295000 GPIO 4 P15.11 LP / PU1 / VEXT -3983000 -4186500 GPIO 5 P15.4 MP / PU1 / VEXT -4053000 -4295000 GPIO 6 P15.12 LP / PU1 / VEXT -3863000 -4186500 GPIO 7 P15.1 LP / PU1 / VEXT -3923000 -4295000 GPIO 8 P15.13 LP / PU1 / VEXT -3753000 -4186500 GPIO 9 VSS Vx -3808000 -4295000 Must be bonded to VSS 10 P15.14 MP / PU1 / VEXT -3603000 -4186500 GPIO 11 P15.3 MP / PU1 / VEXT -3683000 -4295000 GPIO 12 P15.15 MP / PU1 / VEXT -3443000 -4186500 GPIO Data Sheet TOC-295 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC29x Bare Die Pad Definition Table 2-74 TC29x Bare Die Pad List (cont’d) Number Pad Name Pad Type 13 P15.5 14 Y Comment MP / PU1 / VEXT -3523000 -4295000 GPIO P15.6 MP / PU1 / VEXT -3283000 -4186500 GPIO 15 P15.7 MP / PU1 / VEXT -3363000 -4295000 GPIO 16 P15.8 MP / PU1 / VEXT -3153000 -4186500 GPIO 17 VEXT Vx -3218000 -4295000 Must be bonded to VEXT 18 P14.1 MP / PU1 / VEXT -3073000 -4295000 GPIO 19 P14.0 MP+ / PU1 / VEXT -2983000 -4186500 GPIO 20 P14.3 LP / PU1 / VEXT -2843000 -4186500 GPIO 21 P14.2 LP / PU1 / VEXT -2903000 -4295000 Must be bonded to VEXT if EVR13 active. Must be bonded to VSS if EVR13 inactive. 22 P14.4 LP / PU1 / VEXT -2733000 -4186500 GPIO 23 VSS Vx -2788000 -4295000 Must be bonded to VSS 24 VDD Vx -2674000 -4295000 Must be bonded to VDD 25 VSS Vx -2574000 -4295000 Must be bonded to VSS 26 VDDFL3 Vx -2505000 -4186500 Must be bonded to VDDP3 27 P14.11 LP / PU1 / VEXT -2380000 -4186500 GPIO 28 VDDFL3 Vx -2437500 -4295000 Must be bonded to VDDP3 29 P14.5 MP+ / PU1 / VEXT -2300000 -4295000 GPIO 30 P14.12 LP / PU1 / VEXT -2220000 -4186500 GPIO 31 P14.6 MP+ / PU1 / VEXT -2140000 -4295000 GPIO 32 P14.13 MP+ / PU1 / VEXT -2040000 -4186500 GPIO 33 P14.7 LP / PU1 / VEXT -1960000 -4295000 GPIO 34 P14.14 MP+ / PU1 / VEXT -1880000 -4186500 GPIO 35 VEXT Vx -1805000 -4295000 Must be bonded to VEXT 36 P14.8 LP / PU1 / VEXT -1750000 -4186500 GPIO 37 P14.9 MP+ / PU1 / VEXT -1670000 -4295000 GPIO 38 P14.15 LP / PU1 / VEXT -1590000 -4186500 GPIO 39 P14.10 MP+ / PU1 / VEXT -1510000 -4295000 GPIO 40 VDDFL3 Vx -1410000 -4186500 Must be bonded to VDDP3 41 VSS Vx -1345000 -4295000 Must be bonded to VSS 42 P13.0 LVDSM_N / PU1 -1270000 / VEXT -4186500 GPIO Data Sheet X TOC-296 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC29x Bare Die Pad Definition Table 2-74 TC29x Bare Die Pad List (cont’d) Number Pad Name Pad Type 43 P13.1 44 Y Comment LVDSM_P / PU1 -940000 / VEXT -4186500 GPIO VEXT Vx -865000 -4295000 Must be bonded to VEXT 45 P13.2 LVDSM_N / PU1 -790000 / VEXT -4186500 GPIO 46 P13.3 LVDSM_P / PU1 -460000 / VEXT -4186500 GPIO 47 VSS Vx -385000 -4295000 Must be bonded to VSS 48 P13.4 LVDSM_N / PU1 -310000 / VEXT -4186500 GPIO 49 P13.5 LVDSM_P / PU1 20000 / VEXT -4186500 GPIO 50 VEXT Vx -4295000 Must be bonded to VEXT 51 P13.6 LVDSM_N / PU1 170000 / VEXT -4186500 GPIO 52 P13.7 LVDSM_P / PU1 500000 / VEXT -4186500 GPIO 53 P13.11 LP / PU1 / VEXT 580000 -4295000 GPIO 54 P13.12 LP / PU1 / VEXT 640000 -4186500 GPIO 55 VDDP3 Vx 697500 -4295000 Must be bonded to VDDP3 56 VDDP3 Vx 765000 -4186500 Must be bonded to VDDP3 57 VEXT Vx 830000 -4295000 Must be bonded to VEXT 58 VEXT Vx 880000 -4186500 Must be bonded to VEXT 59 VDD Vx 955000 -4295000 Must be bonded to VDD 60 VSS Vx 1055000 -4295000 Must be bonded to VSS 61 P13.13 LP / PU1 / VEXT 1135000 -4186500 GPIO 62 P13.9 MP / PU1 / VEXT 1205000 -4295000 GPIO 63 P13.14 LP / PU1 / VEXT 1275000 -4186500 GPIO 64 VEXT Vx 1330000 -4295000 Must be bonded to VEXT 65 P13.10 LP / PU1 / VEXT 1385000 -4186500 GPIO 66 VDDFL3 Vx 1455000 -4295000 Must be bonded to VDDP3 67 VSS Vx 1575000 -4295000 Must be bonded to VSS (Double Pad / Center of Elephant Pad Opening) 68 VDDFL3 Vx 1542500 -4186500 Must be bonded to VDDP3 69 P13.15 LP / PU1 / VEXT 1660000 -4186500 GPIO 70 P12.0 LP / PU1 / VFLEX 1790000 -4186500 GPIO 71 P12.1 LP / PU1 / VFLEX 1850000 -4295000 GPIO Data Sheet X 95000 TOC-297 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC29x Bare Die Pad Definition Table 2-74 TC29x Bare Die Pad List (cont’d) Number Pad Name Pad Type X Y Comment 72 P11.0 MP+ / PU1 / VFLEX 1930000 -4186500 GPIO 73 VSS Vx 2005000 -4295000 Must be bonded to VSS 74 P11.1 MP+ / PU1 / VFLEX 2080000 -4186500 GPIO 75 VFLEX Vx 2155000 -4295000 Digital Power Supply for VFLEX Ports / Pads (5V / 3.3V) 76 P11.2 MPR/ PU1 / VFLEX 2230000 -4186500 GPIO 77 P11.4 MP+ / PU1 / VFLEX 2330000 -4295000 GPIO 78 P11.3 MPR/ PU1 / VFLEX 2430000 -4186500 GPIO 79 P11.5 LP / PU1 / VFLEX 2510000 -4295000 GPIO 80 P11.6 MPR/ PU1 / VFLEX 2590000 -4186500 GPIO 81 VSS Vx 2665000 -4295000 Must be bonded to VSS 82 P11.9 MP+ / PU1 / VFLEX 2740000 -4186500 GPIO 83 P11.7 LP / PU1 / VFLEX 2820000 -4295000 GPIO 84 VFLEX Vx 2935000 -4295000 Digital Power Supply for VFLEX Ports / Pads (5V / 3.3V) 85 P11.8 LP / PU1 / VFLEX 2880000 -4186500 GPIO 86 P11.13 LP / PU1 / VFLEX 3050000 -4295000 GPIO 87 P11.10 LP / PU1 / VFLEX 2990000 -4186500 GPIO 88 P11.11 MP+ / PU1 / VFLEX 3130000 -4186500 GPIO 89 VSS Vx 3215000 -4295000 Must be bonded to VSS 90 P11.12 MPR/ PU1 / VFLEX 3300000 -4186500 GPIO 91 P11.14 LP / PU1 / VFLEX 3390000 -4295000 GPIO 92 P11.15 LP / PU1 / VFLEX 3460000 -4186500 GPIO 93 P10.0 LP / PU1 / VEXT 3610000 -4295000 GPIO 94 VEXT Vx -4295000 Must be bonded to VEXT Data Sheet 3775000 TOC-298 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC29x Bare Die Pad Definition Table 2-74 TC29x Bare Die Pad List (cont’d) Number Pad Name Pad Type 95 P10.9 96 Y Comment LP / PU1 / VEXT 3680000 -4186500 GPIO P10.1 MP+ / PU1 / VEXT 3865000 -4186500 GPIO 97 P10.3 MP / PU1 / VEXT 3970000 -4295000 GPIO 98 P10.4 MP+ / PU1 / VEXT 4150000 -4295000 GPIO 99 P10.10 LP / PU1 / VEXT 4055000 -4186500 GPIO 100 P10.2 MP / PU1 / VEXT 4310000 -4295000 GPIO 101 P10.11 LP / PU1 / VEXT 4240000 -4186500 GPIO 102 P10.13 LP / PU1 / VEXT 4419500 -4050000 GPIO 103 VSS Vx 4528000 -4105000 Must be bonded to VSS 104 P10.14 LP / PU1 / VEXT 4419500 -3930000 GPIO 105 P10.5 LP / PU1 / VEXT 4528000 -3990000 GPIO 106 P10.15 LP / PU1 / VEXT 4419500 -3810000 GPIO 107 P10.6 LP / PU1 / VEXT 4528000 -3870000 GPIO 108 P02.13 LP / PU1 / VEXT 4419500 -3690000 GPIO 109 P10.8 LP / PU1 / VEXT 4528000 -3750000 GPIO 110 P10.7 LP / PU1 / VEXT 4419500 -3580000 GPIO 111 VEXT Vx 4528000 -3635000 Must be bonded to VEXT 112 VDD Vx 4528000 -3520000 Must be bonded to VDD 113 P02.12 LP / PU1 / VEXT 4419500 -3360000 GPIO 114 VSS Vx 4528000 -3420000 Must be bonded to VSS 115 P02.0 MP+ / PU1 / VEXT 4528000 -3280000 GPIO 116 P02.14 LP / PU1 / VEXT 4419500 -3200000 GPIO 117 P02.1 LP / PU1 / VEXT 4528000 -3140000 GPIO 118 P02.15 MP+ / PU1 / VEXT 4419500 -3060000 GPIO 119 VSS Vx 4528000 -2985000 Must be bonded to VSS 120 P02.2 MP+ / PU1 / VEXT 4419500 -2910000 GPIO 121 P02.3 LP / PU1 / VEXT 4528000 -2830000 GPIO 122 P02.4 MP+ / PU1 / VEXT 4419500 -2750000 GPIO 123 P02.9 LP / PU1 / VEXT 4528000 -2670000 GPIO 124 P02.5 MP+ / PU1 / VEXT 4419500 -2590000 GPIO 125 P02.10 LP / PU1 / VEXT 4528000 -2510000 GPIO 126 P02.6 MP / PU1 / VEXT 4419500 -2440000 GPIO 127 VEXT Vx -2375000 Must be bonded to VEXT Data Sheet X 4528000 TOC-299 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC29x Bare Die Pad Definition Table 2-74 TC29x Bare Die Pad List (cont’d) Number Pad Name Pad Type 128 P02.7 129 Y Comment MP / PU1 / VEXT 4419500 -2310000 GPIO P02.11 LP / PU1 / VEXT 4528000 -2240000 GPIO 130 P02.8 LP / PU1 / VEXT 4419500 -2180000 GPIO 131 VDD Vx 4528000 -2095000 Must be bonded to VDD 132 VSS Vx 4528000 -1995000 Must be bonded to VSS 133 P01.0 LP / PU1 / VEXT 4419500 -1937500 GPIO 134 VSS Vx 4528000 -1910000 Must be bonded to VSS (Double Pad / Center of Elephant Pad Opening) 135 VDD Vx 4528000 -1780000 Must be bonded to VDD 136 P01.2 LP / PU1 / VEXT 4419500 -1715000 GPIO 137 VSS Vx 4528000 -1660000 Must be bonded to VSS 138 P01.1 LP / PU1 / VEXT 4419500 -1605000 GPIO 139 P01.3 LP / PU1 / VEXT 4528000 -1545000 GPIO 140 P01.8 LP / PU1 / VEXT 4419500 -1485000 GPIO 141 P01.4 LP / PU1 / VEXT 4528000 -1425000 GPIO 142 P01.9 LP / PU1 / VEXT 4419500 -1365000 GPIO 143 P01.5 LP / PU1 / VEXT 4528000 -1305000 GPIO 144 P01.10 LP / PU1 / VEXT 4419500 -1245000 GPIO 145 VEXT Vx 4528000 -1190000 Must be bonded to VEXT 146 P01.11 LP / PU1 / VEXT 4419500 -1135000 GPIO 147 P01.6 MP / PU1 / VEXT 4528000 -1065000 GPIO 148 P01.12 MP+ / PU1 / VEXT 4419500 -975000 GPIO 149 P01.7 MP / PU1 / VEXT 4528000 -885000 GPIO 150 VDD Vx 4528000 -785000 Must be bonded to VDD 151 VSS Vx 4528000 -685000 Must be bonded to VSS 152 P01.13 MP+ / PU1 / VEXT 4419500 -610000 GPIO 153 VSS Vx 4528000 -535000 Must be bonded to VSS 154 P01.14 MP+ / PU1 / VEXT 4419500 -460000 GPIO 155 Reserved Vx 4528000 -385000 Must be bonded to VSS 156 P01.15 LP / PU1 / VEXT 4419500 -330000 GPIO 157 VEXT Vx 4528000 -265000 Must be bonded to VEXT 158 P00.13 MP+ / PU1 / VEXT 4419500 -190000 GPIO 159 P00.0 MP / PU1 / VEXT 4528000 -100000 GPIO 160 P00.14 LP / PU1 / VEXT 4419500 -30000 GPIO 161 VSS Vx 25000 Must be bonded to VSS Data Sheet X 4528000 TOC-300 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC29x Bare Die Pad Definition Table 2-74 TC29x Bare Die Pad List (cont’d) Number Pad Name Pad Type X Y Comment 162 P00.15 MP+ / PU1 / VEXT 4419500 100000 GPIO 163 P00.1 (VADC7.5 D / DS5NA) 4419500 250000 Analog input 164 P00.2 (VADC7.4 D / DS5PA) 4528000 310000 Analog input 165 P00.3 (VADC7.3) D 4419500 370000 Analog input 166 VSS 4528000 425000 Must be bonded to VSS 167 P00.4 (VADC7.2) D 4419500 480000 Analog input 168 P00.5 (VADC7.1) D 4528000 540000 Analog input 169 P00.6 (VADC7.0) D 4419500 600000 Analog input 170 VEXT 4528000 655000 Must be bonded to VEXT 171 P00.7 (VADC6.5 D / DS4NA) 4419500 710000 Analog input 172 P00.8 (VADC6.4 D / DS4PA) 4528000 770000 Analog input 173 P00.9 (VADC6.3) D 4419500 830000 Analog input 174 P00.10 (VADC6.2) D 4528000 890000 Analog input 175 P00.11 (VADC6.1) D 4419500 950000 Analog input 176 VSS Vx 4528000 1005000 Must be bonded to VSS 177 P00.12 (VADC6.0) D 4419500 1060000 Analog input 178 VDD Vx 4528000 1115000 Must be bonded to VDD 179 VSS Vx 4528000 1215000 Must be bonded to VSS 180 VEXT Vx 4419500 1265000 Must be bonded to VEXT 181 VSS Vx 4528000 1315000 Must be bonded to VSS 182 VDD Vx 4528000 1415000 Must be bonded to VDD 183 VAREF4 Vx 4528000 1535000 Positive Analog Reference Voltage 4 184 VAGND4 Vx 4419500 1585000 Negative Analog Reference Voltage 4 185 VDDM Vx 4528000 1635000 Must be bonded to VEXT 186 AN47 (VADC5.7 / S DS3ND) 4419500 1685000 Analog input 187 AN46 (VADC5.6 / S DS3PD) 4528000 1735000 Analog input 188 AN45 (VADC5.5 / S DS3NC) 4419500 1785000 Analog input Data Sheet Vx Vx TOC-301 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC29x Bare Die Pad Definition Table 2-74 TC29x Bare Die Pad List (cont’d) Number Pad Name 189 X Y Comment AN44 (VADC5.4 / S DS3PC) 4528000 1835000 Analog input 190 AN43 (VADC5.3) D 4419500 1885000 Analog input (with pull down diagnostics) 191 AN42 (VADC5.2) D 4528000 1935000 Analog input 192 AN41 (VADC5.1) D 4419500 1985000 Analog input 193 AN40 (VADC5.0) D 4528000 2035000 Analog input 194 AN38 (VADC4.6 / S DS3PB), P40.8 (SENT8A) 4528000 2135000 Analog input, GPI (SENT) 195 AN39 (VADC4.7 / S DS3NB), P40.9 (SENT9A) 4419500 2085000 Analog input, GPI (SENT) 196 AN36 (VADC4.4 / S DS3PA), P40.6 (SENT6A) 4528000 2235000 Analog input, GPI (SENT) 197 AN37 (VADC4.5 / S DS3NA), P40.7 (SENT7A) 4419500 2185000 Analog input, GPI (SENT) 198 AN34 (VADC4.2) D 4528000 2335000 Analog input 199 AN35 (VADC4.3) D 4419500 2285000 Analog input (with pull down diagnostics) 200 AN32 S (VADC4.0), P40.4 (SENT4A) 4528000 2435000 Analog input, GPI (SENT) 201 AN33 S (VADC4.1), P40.5 (SENT5A) 4419500 2385000 Analog input, GPI (SENT) 202 S AN70 (VADC10.6 / DS9PA), P40.13 (SENT13A) 4528000 2535000 Analog input, GPI (SENT) 203 S AN71 (VADC10.7 / DS9NA), P40.14 (SENT14A) 4419500 2485000 Analog input, GPI (SENT) 204 S AN68 (VADC10.4 / DS8PA), P40.11 (SENT11A) 4528000 2635000 Analog input, GPI (SENT) 205 S AN69 (VADC10.5 / DS8NA), P40.12 (SENT12A) 4419500 2585000 Analog input, GPI (SENT) Data Sheet Pad Type TOC-302 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC29x Bare Die Pad Definition Table 2-74 TC29x Bare Die Pad List (cont’d) Number Pad Name Pad Type X Y Comment 206 VDDM Vx 4528000 2735000 Must be bonded to VEXT 207 S AN67 (VADC10.3 / DS8NB), P40.10 (SENT10A) 4419500 2685000 Analog input, GPI (SENT) 208 VSSM Vx 4528000 2835000 Must be bonded to VSS 209 VSS Vx 4419500 2785000 Must be bonded to VSS 210 AN65 (VADC10.1) D 4528000 2935000 Analog input 211 AN66 (VADC10.2 / DS8PB D 4419500 2885000 Analog input 212 AN63 (VADC9.7 / D DS7NB) 4528000 3035000 Analog input 213 AN64 (VADC10.0) D 4419500 2985000 Analog input 214 AN61 (VADC9.5 / D DS7NA) 4528000 3135000 Analog input 215 AN62 (VADC9.6 / D DS7PB) 4419500 3085000 Analog input 216 AN59 (VADC9.3) D 4528000 3235000 Analog input 217 AN60 (VADC9.4 / D DS7PA) 4419500 3185000 Analog input 218 AN57 (VADC9.1) D 4528000 3335000 Analog input 219 AN58 (VADC9.2) D 4419500 3285000 Analog input 220 VAREF3 4528000 3435000 Positive Analog Reference Voltage 3 221 AN56 (VADC9.0) D 4419500 3385000 Analog input 222 VAGND3 Vx 4528000 3535000 Negative Analog Reference Voltage 3 223 VAREF2 Vx 4419500 3485000 Positive Analog Reference Voltage 2 224 AN55 (VADC8.7 / D DS6NB) 4528000 3635000 Analog input 225 VAGND2 4419500 3585000 Negative Analog Reference Voltage 2 226 AN53 (VADC8.5 / D DS6NA) 4528000 3735000 Analog input 227 AN54 (VADC8.6 / D DS6PB) 4419500 3685000 Analog input 228 AN51 (VADC8.3) D 4528000 3835000 Analog input Data Sheet Vx Vx TOC-303 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC29x Bare Die Pad Definition Table 2-74 TC29x Bare Die Pad List (cont’d) Number Pad Name 229 X Y Comment AN52 (VADC8.4 / D DS6PA) 4419500 3785000 Analog input 230 AN49 (VADC8.1) D 4528000 3960000 Analog input 231 AN50 (VADC8.2) D 4419500 3897400 Analog input 232 VDDM 4528000 4085000 Must be bonded to VEXT 233 AN48 (VADC8.0) D 4419500 4022600 Analog input 234 AN31 (VADC3.7) D 4278000 4186500 Analog input 235 VSSM 4328000 4295000 Must be bonded to VSS 236 AN29 (VADC3.5) D 4178000 4186500 Analog input 237 AN30 (VADC3.6) D 4228000 4295000 Analog input 238 AN27 S (VADC3.3), P40.3 (SENT3A) 4078000 4186500 Analog input (with pull down diagnostics), GPI (SENT) 239 AN28 (VADC3.4) D 4128000 4295000 Analog input 240 AN25 (VADC3.1 / S DS2NB), P40.2 (SENT1A) 3978000 4186500 Analog input, GPI (SENT) 241 AN26 S (VADC3.2), P40.2 (SENT2A) 4028000 4295000 Analog input, GPI (SENT) 242 AN23 (VADC2.7) D 3878000 4186500 Analog input 243 AN24 (VADC3.0 / S DS2PB), P40.0 (SENT0A) 3928000 4295000 Analog input, GPI (SENT) 244 AN21 (VADC2.5 / D DS2NA) 3778000 4186500 Analog input 245 AN22 (VADC2.6) D 3828000 4295000 Analog input 246 AN19 (VADC2.3) D 3678000 4186500 Analog input (with pull down diagnostics) 247 AN20 (VADC2.4 / D DS2PA) 3728000 4295000 Analog input 248 AN17 (VADC2.1) D 3578000 4186500 Analog input 249 AN18 (VADC2.2) D 3628000 4295000 Analog input 250 AN15 (VADC1.7) D 3478000 4186500 Analog input 251 AN16 (VADC2.0) D 3528000 4295000 Analog input 252 VAGND0 Vx 3378000 4186500 Negative Analog Reference Voltage 0 253 VAGND1 Vx 3428000 4295000 Negative Analog Reference Voltage 1 254 VAREF0 Vx 3278000 4186500 Positive Analog Reference Voltage 0 Data Sheet Pad Type Vx Vx TOC-304 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC29x Bare Die Pad Definition Table 2-74 TC29x Bare Die Pad List (cont’d) Number Pad Name Pad Type X Y Comment 255 VAREF1 Vx 3328000 4295000 Positive Analog Reference Voltage 1 256 VSS Vx 3178000 4186500 Must be bonded to VSS 257 VSSM Vx 3228000 4295000 Must be bonded to VSS 258 AN14 (VADC1.6) D 3078000 4186500 Analog input 259 VDDM 3128000 4295000 Must be bonded to VEXT 260 AN12 (VADC1.4) D 2978000 4186500 Analog input 261 AN13 (VADC1.5) D 3028000 4295000 Analog input 262 AN10 (VADC1.2) D 2878000 4186500 Analog input 263 AN11 (VADC1.3) D 2928000 4295000 Analog input (with pull down diagnostics) 264 AN8 (VADC1.0) D 2778000 4186500 Analog input 265 AN9 (VADC1.1) D 2828000 4295000 Analog input 266 AN6 (VADC0.6) D 2678000 4186500 Analog input 267 AN7 (VADC0.7) D 2728000 4295000 Analog input (with pull down diagnostics) 268 AN4 (VADC0.4) D 2578000 4186500 Analog input 269 AN5 (VADC0.5) D 2628000 4295000 Analog input 270 AN2 (VADC0.2 / DS0PA) D 2478000 4186500 Analog input 271 AN3 (VADC0.3 / DS0NA) D 2528000 4295000 Analog input 272 AN1 (VADC0.1 / DS1NA) D 2378000 4186500 Analog input 273 VSSM Vx 2428000 4295000 Must be bonded to VSS 274 AN0 (VADC0.0 / DS1PA) D 2278000 4186500 Analog input 275 VDDM Vx 2328000 4295000 Must be bonded to VEXT 276 EVR_OFF Vx 2158000 4295000 Must be bonded to VSS 277 P33.0 LP / PU1 / VEXT 2103000 4186500 GPIO 278 VSS Vx 2048000 4295000 Must be bonded to VSS 279 P33.1 LP / PU1 / VEXT 1993000 4186500 GPIO 280 P34.1 LP / PU1 / VEXT 1933000 4295000 GPIO 281 P33.2 LP / PU1 / VEXT 1873000 4186500 GPIO 282 VSS Vx 1778000 4295000 Must be bonded to VSS 283 VDD Vx 1678000 4295000 Must be bonded to VDD 284 P33.3 LP / PU1 / VEXT 1583000 4186500 GPIO 285 VEXT Vx 1509000 4295000 Must be bonded to VEXT 286 VEXT Vx 1440000 4186500 Must be bonded to VEXT 287 P34.2 LP / PU1 / VEXT 1385000 4295000 GPIO Data Sheet Vx TOC-305 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC29x Bare Die Pad Definition Table 2-74 TC29x Bare Die Pad List (cont’d) Number Pad Name Pad Type 288 P33.4 289 Y Comment LP / PU1 / VEXT 1325000 4186500 GPIO P34.3 LP / PU1 / VEXT 1265000 4295000 GPIO 290 P33.5 LP / PU1 / VEXT 1205000 4186500 GPIO 291 P34.4 LP / PU1 / VEXT 1145000 4295000 GPIO 292 P33.6 LP / PU1 / VEXT 1085000 4186500 GPIO 293 P34.5 LP / PU1 / VEXT 1015000 4295000 GPIO 294 P33.7 LP / PU1 / VEXT 955000 4186500 GPIO 295 P33.8 MP / HighZ / VEXT 885000 4295000 GPIO 296 P33.9 LP / PU1 / VEXT 815000 4186500 GPIO 297 VSS Vx 760000 4295000 Must be bonded to VSS 298 P33.10 MP / PU1 / VEXT 695000 4186500 GPIO 299 P33.14 LP / PU1 / VEXT 625000 4295000 GPIO 300 P33.11 MP / PU1 / VEXT 555000 4186500 GPIO 301 P33.15 LP / PU1 / VEXT 485000 4295000 GPIO 302 P33.12 MP / PU1 / VEXT 415000 4186500 GPIO 303 P32.5 LP / PU1 / VEXT 345000 4295000 GPIO 304 P33.13 MP / PU1 / VEXT 275000 4186500 GPIO 305 P32.6 LP / PU1 / VEXT 205000 4295000 GPIO 306 VGATE3P (LDO) VGATE3P 150000 4186500 Must be bonded to VSS 307 VEXT Vx 96000 4295000 Must be bonded to VEXT 308 P32.0 LP / EVR13 SMPS -> PD, GPIO -> PU1 / VEXT 37000 4186500 GPIO 309 VGATE1N (SMPS) VGATE1N -18000 4295000 Must be bonded to VSS if EVR13 SMPS is not used. Must be bonded to NMOS gate if EVR13 SMPS is used. 310 VGATE1P (SMPS) VGATE1P -68000 4186500 Must be bonded to VEXT if EVR13 SMPS is not used. Must be bonded to PMOS gate if EVR13 SMPS is used. 311 VGATE1P (LDO) VGATE1P -118000 4295000 VGATE1P (LDO) 312 P32.2 LP / PU1 / VEXT -173000 4186500 GPIO 313 VSS Vx -268000 4295000 Must be bonded to VSS 314 VDD Vx -368000 4295000 Must be bonded to VDD 315 P32.3 LP / PU1 / VEXT -463000 4186500 GPIO 316 P32.7 LP / PU1 / VEXT -523000 4295000 GPIO Data Sheet X TOC-306 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC29x Bare Die Pad Definition Table 2-74 TC29x Bare Die Pad List (cont’d) Number Pad Name Pad Type X Y Comment 317 P32.4 MP+ / PU1 / VEXT -603000 4186500 GPIO 318 VSS Vx -678000 4295000 Must be bonded to VSS 319 P31.0 MP / PU1 / VFLEXE -823000 4295000 GPIO 320 P31.1 MP / PU1 / VFLEXE -903000 4186500 GPIO 321 P31.2 MP / PU1 / VFLEXE -983000 4295000 GPIO 322 P31.3 MP / PU1 / VFLEXE -1063000 4186500 GPIO 323 VSS Vx -1128000 4295000 Must be bonded to VSS 324 P31.4 MP / PU1 / VFLEXE -1193000 4186500 GPIO 325 P31.5 MP / PU1 / VFLEXE -1273000 4295000 GPIO 326 P31.6 MP / PU1 / VFLEXE -1353000 4186500 GPIO 327 P31.7 MP / PU1 / VFLEXE -1433000 4295000 GPIO 328 P31.8 MP / PU1 / VFLEXE -1513000 4186500 GPIO 329 VFLEXE Vx -1578000 4295000 Must be bonded to VEXT or VDDP3 330 P31.9 MP / PU1 / VFLEXE -1643000 4186500 GPIO 331 P31.10 MP / PU1 / VFLEXE -1723000 4295000 GPIO 332 P31.14 MP / PU1 / VFLEXE -1803000 4186500 GPIO 333 P31.15 MP / PU1 / VFLEXE -1883000 4295000 GPIO 334 P31.11 MP / PU1 / VFLEXE -1963000 4186500 GPIO 335 VSS Vx -2068000 4295000 Must be bonded to VSS 336 VDD Vx -2168000 4295000 Must be bonded to VDD 337 P31.12 MP / PU1 / VFLEXE -2273000 4186500 GPIO 338 VSS Vx -2338000 4295000 Must be bonded to VSS 339 P31.13 MP / PU1 / VFLEXE -2403000 4186500 GPIO Data Sheet TOC-307 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC29x Bare Die Pad Definition Table 2-74 TC29x Bare Die Pad List (cont’d) Number Pad Name Pad Type X Y Comment 340 P30.0 MP / PU1 / VFLEXE -2483000 4295000 GPIO 341 P30.1 MP / PU1 / VFLEXE -2563000 4186500 GPIO 342 P30.2 MP / PU1 / VFLEXE -2643000 4295000 GPIO 343 VFLEXE Vx -2788000 4295000 Must be bonded to VEXT or VDDP3 344 P30.3 MP / PU1 / VFLEXE -2723000 4186500 GPIO 345 VSS Vx -2918000 4295000 Must be bonded to VSS 346 P30.4 MP / PU1 / VFLEXE -2853000 4186500 GPIO 347 P30.5 MP / PU1 / VFLEXE -2983000 4186500 GPIO 348 P30.6 MP / PU1 / VFLEXE -3063000 4295000 GPIO 349 P30.8 MP / PU1 / VFLEXE -3223000 4295000 GPIO 350 P30.7 MP / PU1 / VFLEXE -3143000 4186500 GPIO 351 VFLEXE Vx -3368000 4295000 Must be bonded to VEXT or VDDP3 352 P30.9 MP / PU1 / VFLEXE -3303000 4186500 GPIO 353 P30.11 MP / PU1 / VFLEXE -3513000 4295000 GPIO 354 P30.10 MP / PU1 / VFLEXE -3433000 4186500 GPIO 355 P30.15 MP / PU1 / VFLEXE -3673000 4295000 GPIO 356 P30.12 MP / PU1 / VFLEXE -3593000 4186500 GPIO 357 VSS Vx -3818000 4295000 Must be bonded to VSS 358 P30.13 MP / PU1 / VFLEXE -3753000 4186500 GPIO 359 P26.0 LP / PU1 / VFLEXE -3953000 4295000 GPIO 360 P30.14 MP / PU1 / VFLEXE -3883000 4186500 GPIO 361 VSS Vx -4098000 4295000 Must be bonded to VSS (Double Pad / Center of Elephant Pad Opening) Data Sheet TOC-308 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC29x Bare Die Pad Definition Table 2-74 TC29x Bare Die Pad List (cont’d) Number Pad Name Pad Type 362 P25.0 363 Y Comment A2 / PU1 / VEBU -4078000 4186500 GPIO P25.2 A2 / PU1 / VEBU -4228000 4295000 GPIO 364 P25.1 A2 / PU1 / VEBU -4178000 4186500 GPIO 365 P25.4 A2 / PU1 / VEBU -4338000 4295000 GPIO 366 P25.3 A2 / PU1 / VEBU -4288000 4186500 GPIO 367 P25.5 A2 / PU1 / VEBU -4419500 4105000 GPIO 368 P25.7 A2 / PU1 / VEBU -4419500 4005000 GPIO 369 VEBU Vx -4528000 4055000 Must be bonded to VEXT or VDDP3 370 P25.8 A2 / PU1 / VEBU -4419500 3905000 GPIO 371 VSS Vx -4528000 3955000 Must be bonded to VSS 372 P25.10 A2 / PU1 / VEBU -4419500 3805000 GPIO 373 P25.9 A2 / PU1 / VEBU -4528000 3855000 GPIO 374 VSS Vx -4528000 3755000 Must be bonded to VSS 375 P25.11 A2 / PU1 / VEBU -4419500 3605000 GPIO 376 VDD Vx -4528000 3655000 Must be bonded to VDD 377 P25.13 A2 / PU1 / VEBU -4419500 3505000 GPIO 378 P25.12 A2 / PU1 / VEBU -4528000 3555000 GPIO 379 P25.14 A2 / PU1 / VEBU -4419500 3405000 GPIO 380 VEBU Vx -4528000 3455000 Must be bonded to VEXT or VDDP3 381 P25.6 A2 / PU1 / VEBU -4419500 3305000 GPIO 382 P25.15 A2 / PU1 / VEBU -4528000 3355000 GPIO 383 P24.1 A2 / PU1 / VEBU -4419500 3205000 GPIO 384 P24.0 A2 / PU1 / VEBU -4528000 3255000 GPIO 385 P24.2 A2 / PU1 / VEBU -4419500 3105000 GPIO 386 VSS Vx -4528000 3155000 Must be bonded to VSS 387 P24.4 A2 / PU1 / VEBU -4419500 3005000 GPIO 388 P24.3 A2 / PU1 / VEBU -4528000 3055000 GPIO 389 P24.6 A2 / PU1 / VEBU -4419500 2905000 GPIO 390 P24.5 A2 / PU1 / VEBU -4528000 2955000 GPIO 391 VSS Vx -4528000 2845000 Must be bonded to VSS 392 P24.7 A2 / PU1 / VEBU -4419500 2685000 GPIO 393 VDD Vx -4528000 2745000 Must be bonded to VDD 394 P24.8 A2 / PU1 / VEBU -4419500 2585000 GPIO 395 VEBU Vx -4528000 2635000 Must be bonded to VEXT or VDDP3 396 P24.10 A2 / PU1 / VEBU -4419500 2485000 GPIO 397 P24.9 A2 / PU1 / VEBU -4528000 2535000 GPIO Data Sheet X TOC-309 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC29x Bare Die Pad Definition Table 2-74 TC29x Bare Die Pad List (cont’d) Number Pad Name Pad Type 398 P24.12 399 Y Comment A2 / PU1 / VEBU -4419500 2385000 GPIO P24.11 A2 / PU1 / VEBU -4528000 2435000 GPIO 400 P24.13 A2 / PU1 / VEBU -4419500 2285000 GPIO 401 VSS Vx -4528000 2335000 Must be bonded to VSS 402 P24.15 A2 / PU1 / VEBU -4419500 2185000 GPIO 403 P24.14 A2 / PU1 / VEBU -4528000 2235000 GPIO 404 P23.5 MP+ / PU1 / VEXT -4419500 2040000 GPIO 405 VSS Vx -4528000 1965000 Must be bonded to VSS 406 P23.0 LP / PU1 / VEXT -4419500 1910000 GPIO 407 VEXT Vx -4528000 1855000 Must be bonded to VEXT 408 P23.1 MP+ / PU1 / VEXT -4419500 1780000 GPIO 409 VDD Vx -4528000 1695000 Must be bonded to VDD 410 VSS Vx -4528000 1595000 Must be bonded to VSS 411 P23.2 LP / PU1 / VEXT -4419500 1510000 GPIO 412 P23.6 LP / PU1 / VEXT -4528000 1450000 GPIO 413 P23.3 LP / PU1 / VEXT -4419500 1390000 GPIO 414 P23.7 LP / PU1 / VEXT -4528000 1330000 GPIO 415 P23.4 MP+ / PU1 / VEXT -4419500 1250000 GPIO 416 VSS Vx -4528000 1175000 Must be bonded to VSS 417 P22.0 LVDSM_N / PU1 -4419500 / VEXT 1100000 GPIO 418 P22.1 LVDSM_P / PU1 -4419500 / VEXT 770000 GPIO 419 VSS Vx -4528000 688000 Must be bonded to VSS 420 VDD Vx -4528000 588000 Must be bonded to VDD 421 P22.2 LVDSM_N / PU1 -4419500 / VEXT 513000 GPIO 422 P22.3 LVDSM_P / PU1 -4419500 / VEXT 183000 GPIO 423 VEXT Vx 108000 Must be bonded to VEXT 424 P22.4 LP / PU1 / VEXT -4419500 53000 GPIO 425 VSS Vx -4528000 -2000 Must be bonded to VSS 426 VDD Vx -4528000 -102000 Must be bonded to VDD 427 P22.5 LP / PU1 / VEXT -4419500 -157000 GPIO 428 P22.7 LP / PU1 / VEXT -4528000 -217000 GPIO 429 P22.6 LP / PU1 / VEXT -4419500 -277000 GPIO 430 VSS Vx -332000 Must be bonded to VSS Data Sheet X -4528000 -4528000 TOC-310 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC29x Bare Die Pad Definition Table 2-74 TC29x Bare Die Pad List (cont’d) Number Pad Name Pad Type 431 P22.8 432 Y Comment LP / PU1 / VEXT -4419500 -387000 GPIO P22.9 LP / PU1 / VEXT -4528000 -447000 GPIO 433 P22.10 LP / PU1 / VEXT -4419500 -507000 GPIO 434 P22.11 LP / PU1 / VEXT -4528000 -567000 GPIO 435 VDDOSC Vx -4528000 -702000 Must be bonded to VSS 436 VSSOSC Vx -4528000 -802000 Must be bonded to VSS 437 XTAL1 XTAL1 -4419500 -909500 Main Oscillator/PLL/Clock Generator Input. Must be bonded to external quartz or resonator. 438 XTAL2 XTAL2 -4419500 -1009500 Main Oscillator/PLL/Clock Generator Input. Must be bonded to external quartz or resonator. 439 VSSOSC Vx -4528000 -1117000 Must be bonded to VSS 440 VDDOSC3 Vx -4419500 -1167000 Must be bonded to VDDP3 441 VDDP3 Vx -4528000 -1257000 Must be bonded to VDDP3 442 P21.0 LVDSH_N / PU1 -4419500 / VDDP3 -1362500 GPIO 443 P21.1 LVDSH_P / PU1 -4419500 / VDDP3 -1462500 GPIO 444 VSSP Vx -4528000 -1525000 Must be bonded to VSS 445 P21.2 LVDSH_N / PU1 -4419500 / VDDP3 -1587500 GPIO 446 P21.3 LVDSH_P / PU1 -4419500 / VDDP3 -1687500 GPIO 447 VDDP3 Vx -4528000 -1750000 Must be bonded to VDDP3 448 P21.4 LVDSH_N / PU1 -4419500 / VDDP3 -1824500 GPIO 449 VSS Vx -4528000 -2020000 Must be bonded to VSS (Double Pad / Center of Elephant Pad Opening) 450 P21.5 LVDSH_P / PU1 -4419500 / VDDP3 -1975500 GPIO 451 VDD Vx -4528000 -2150000 Must be bonded to VDD 452 VSSP Vx -4528000 -2260000 Must be bonded to VSS 453 P21.6 A2 / PU / VDDP3 -4419500 -2210000 GPIO, TDI 454 VDDP3 Vx -4528000 -2360000 Must be bonded to VDDP3 455 TMS /DAP1 A2 / PD / VDDP3 -4419500 -2310000 JTAG Module State Machine Control Input / Device Access Port Line 1 Data Sheet X TOC-311 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC29x Bare Die Pad Definition Table 2-74 TC29x Bare Die Pad List (cont’d) Number Pad Name Pad Type 456 TCK /DAP0 457 X Y Comment A2 / PD / VDDP3 -4528000 -2460000 JTAG Module Clock Input / Device Access Port Line 0 P21.7 A2 / PU / VDDP3 -4419500 -2410000 GPIO, TDO 458 TRST (N) A2 / PD / VDDP3 -4419500 -2520000 JTAG Module Reset/Enable Input 459 Reserved Vx -4528000 -2650000 Must be bonded to VSS 460 VEXT Vx -4528000 -2780000 Must be bonded to VEXT 461 P20.0 MP / PU1 / VEXT -4419500 -2715000 GPIO 462 VSS Vx -4528000 -2890000 Must be bonded to VSS 463 P20.1 LP / PU1 / VEXT -4419500 -2835000 GPIO 464 PORST (N) PORST / PD / VEXT -4528000 -3007500 Power On Reset Input. Additional strong PD in case of power fail. 465 P20.2 LP / PU1 / VEXT -4419500 -2940000 Testmode pin must be bonded 466 ESR1 (N) /EVRWUP MP / PU1 / VEXT -4528000 -3150000 External System Request Reset 1. Default NMI function. EVR Wakeup Pin. 467 P20.3 LP / PU1 / VEXT -4419500 -3080000 GPIO 468 ESR0 (N) /EVRWUP MP / OD -4528000 -3290000 External System Request Reset 0. Default configuration during and after reset is open-drain driver. The driver drives low during power-on reset. EVR Wakeup Pin. 469 P20.7 LP / PU1 / VEXT -4419500 -3220000 GPIO 470 VEXT Vx -4528000 -3435000 Must be bonded to VEXT 471 P20.8 MP / PU1 / VEXT -4419500 -3370000 GPIO 472 P20.6 LP / PU1 / VEXT -4528000 -3590000 GPIO 473 P20.10 MP / PU1 / VEXT -4419500 -3520000 GPIO 474 P20.9 LP / PU1 / VEXT -4528000 -3750000 GPIO 475 P20.11 MP / PU1 / VEXT -4419500 -3680000 GPIO 476 VSS Vx -4528000 -3905000 Must be bonded to VSS 477 P20.12 MP / PU1 / VEXT -4419500 -3820000 GPIO 478 P20.14 MP / PU1 / VEXT -4528000 -4080000 GPIO 479 P20.13 MP / PU1 / VEXT -4419500 -3990000 GPIO 480 P15.0 LP / PU1 / VEXT -4263000 -4186500 GPIO Legend: Column “Number”: Running number of pads in the pad frame Data Sheet TOC-312 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC29x Bare Die Pad Definition Column “Name”: Symbolic name of the pad. The functions mapped on GPIO pads “Px.y” are described in the User’s Manual chapter ”General Purpose I/O Ports and Peripheral I/O LInes (Ports)” Column “Type”: LP = Pad class LP (5V/3.3V, Class LP parameters for digital input / output and class D parameters for analog input function) MP = Pad class MP (5V/3.3V) MP+ = Pad class MP+ (5V/3.3V) MPR = Pad class MPR (5V/3.3V) A2 = Pad class A2 (3.3V) LVDSM = Pad class LVDSM (5V/3.3V) LVDSH = Pad class LVDSH (3.3V) S = Pad class S (Class S parameters for digital input and class D parameters for analog input function) D = Pad class D (VADC / DSADC) PU = with pull-up device connected during reset (PORST = 0) PU1 = with pull-up device connected during reset (PORST = 0)1) 2) 3) PD = with pull-down device connected during reset (PORST = 0) PD1 = with pull-down device connected during reset (PORST = 0)1) 2) 3) PX = Behavior depends on usage: PD in EVR13 SMPS Mode and PU1 in GPIO Mode OD = open drain during reset (PORST = 0) HighZ = tri-state during reset (PORST = 0) PORST = PORST input pad XTAL1 = XTAL1 input pad XTAL2 = XTAL2 input pad VGATE1P = VGATE1P VGATE3P = VGATE3P Vx = Supply NC = These pins are reserved for future extensions and shall not be connected externally NC1 = These pins are not connected on package level and will not be used for future extensions NCVDDPSB = This pin has a different functionality in an Production Device and an Emulation Device. For details pls. see Pin/Ball description of this pin. NCVDDSB = This pin has a different functionality in an Production Device and an Emulation Device. For details pls. see Pin/Ball description of this pin. Column “X” / “Y”: Pad opening center coordinates 2.4.1 Pad Openings Two different pad openings are used: 1) The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG[6] (P14.4). HWCFG[6] has a weak internal pull-up active at start-up if the pin is left unconnected.See also User´s Manual, “Introduction Chapter”, “General Purpose I/O Ports and Peripheral I/O Lines”, Figure: “Default state of port pins during and after reset”. 2) If HWCFG[6] is left unconnected or is externally pulled high, weak internal pull-ups are active at GPIOs (Px.y) pins during and after reset. Exceptions are P33.8 (HighZ), P40.x (default configuration during and after reset: analog inputs, port input funtion disabled), ESR0, P21.6 / P21.7 (port pins overlayed with JTAG functionality). 3) If HWCFG[6] is connected to ground, port pins are predominantly in HighZ during and after reset. Exceptions are P33.8 (HighZ), P40.x (default configuration during and after reset: analog inputs, port input funtion disabled), ESR0, P21.6 / P21.7 (port pins overlayed with JTAG functionality). Data Sheet TOC-313 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC29x Bare Die Pad Definition • Standard Pad Opening is 70um x 75um where 70um is the width of the opening (width as seen from the die side) and 75um is the depth of the opening (from the die side into the silicon). • Double Pad or Elephant Pad Opening is 130um x 75um where 130um is the width of the opening (width as seen from the die side) and 75um is the depth of the opening (from the die side into the silicon). Double Pads are used only for supply and can be identified by the words ´Double Pad´ or ´Elephant Pad´ in the Comment column. 2.4.2 Emergency Stop Function The Emergency Stop function can be used to force GPIOs (General Purpose Inputs/Outputs) via an external input signal (EMGSTOPA or EMGSTOPB) into a defined state: • Input state and • PU or HighZ depending on HWCFG[6] level latched during Porst active Control of the Emergency Stop function: • The Emergency Stop function can be enabled/disabled in the SCU (see chapter “SCU”, “Emergency Stop Control”) • The Emergency Stop input signal, EMGSTOPA (P33.8) / EMGSTOPB (P21.2) , can selected in the SCU (see chapter “SCU”, “Emergency Stop Control”) • On port level, each GPIO can be enabled/disabled for the Emergency Stop function via the Px_ESR (Port x Emergency Stop) registers in the port control logic (see chapter “General Purpose I/O Ports and Peripheral I/O Lines”, “Emergency Stop Register”). The Emergency Stop function is available for all GPIO Ports with the following exceptions: • Not available for P20.2 (General Purpose Input/GPI only, overlayed with Testmode) • Not available for P40.x (analoge input ANx overlayed with GPI) • Not available for P32.0 EVR13 SMPS mode. • Not available for dedicated I/O without General Purpose Output function (e.g ESRx, TMS, TCK) The Emergency Stop function can be overruled on the following GPIO Ports: • P00.x and P02.x: Emergency Stop can be overruled by the 8-Bit Standby Controller (SBR), if implemented. Overruling can be disabled via the control registers P00_SCR / P02_SCR (see chapter “General Purpose I/O Ports and Peripheral I/O Lines”, P00 / P01) • P00.x: Emergency Stop can be overruled by the VADC. Overruling can be disabled via the control register P00_SCR (see chapter “General Purpose I/O Ports and Peripheral I/O Lines”, P00) • P14.0 and P14.1: Emergency Stop can be overruled in the DXCPL mode (DAP over can physical layer mode). No Overruling in the DXCM (Debug over can message) mode • P21.6: Emergency Stop can be overruled in JTAG mode if this pin is used as TDI • P21.7: Emergency Stop can be overruled in JTAG or Three Pin DAP mode • P20.0: Emergency Stop can be overruled in JTAG mode if this GPIO is used as TDI • P33.8: Emergency Stop can be overruled if this pin is used as safety output pin (SMUFSP) 2.4.3 Data Sheet Pull-Up/Pull-Down Reset Behavior of the Pins TOC-314 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Package and Pinning DefinitionsTC29x Bare Die Pad Definition Table 2-75 List of Pull-Up/Pull-Down Reset Behavior of the Pins Pins PORST = 0 all GPIOs Pull-up if HWCFG[6] = 1 or High-Z if HWCFG[6] = 0 TDI, TESTMODE Pull-up 1) PORST Pull-down with IPORST relevant TRST, TCK, TMS Pull-down ESR0 The open-drain driver is used to drive low.2) ESR1 Pull-up3) TDO Pull-up 1) 2) 3) 4) PORST = 1 Pull-down with IPDLI relevant Pull-up3) High-Z/Pull-up4) Pull-down with IPORST relevant is always activated when a primary supply monitor detects a violation. Valid additionally after deactivation of PORST until the internal reset phase has finished. See the SCU chapter for details. See the SCU_IOCR register description. Depends on JTAG/DAP selection with TRST. In case of leakage test (PORST = 0 and TESTMODE = 0), the pull-down of the TRST pin is switched off. In case of an user application (TESTMODE = 1), the pull-down of the TRST is always switched on. Data Sheet TOC-315 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationParameter Interpretation 3 Electrical Specification 3.1 Parameter Interpretation The parameters listed in this section partly represent the characteristics of the TC290 / TC297 / TC298 / TC299 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are marked with an two-letter abbreviation in column “Symbol”: • CC Such parameters indicate Controller Characteristics which are a distinctive feature of the TC290 / TC297 / TC298 / TC299 and must be regarded for a system design. • SR Such parameters indicate System Requirements which must provided by the microcontroller system in which the TC290 / TC297 / TC298 / TC299 designed in. Data Sheet 3-316 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationAbsolute Maximum Ratings 3.2 Absolute Maximum Ratings Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the Operational Conditions of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 3-1 Absolute Maximum Ratings Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition upto 65h @ TJ = 150°C; upto 15h @ TJ = 170°C Storage Temperature TST SR -65 - 170 °C Voltage at VDD power supply pins with respect to VSS 1) VDD SR - - 1.9 V VDDP3 SR Voltage at VDDP3 and VDDFL3 power supply pins with respect to VSS 1) - - 4.43 V Voltage at VDDM, VEXT and VFLEX power supply pins with respect to VSS 1) VDDM SR - - 7.0 V Voltage on any class A2 and LVDSH input pin with respect to VSS 1)2) VIN SR -0.5 - min( V Voltage on all other input pins with respect to VSS 1)2) VIN SR 0.6 , 4.23 ) Input current on any pin during IIN SR overload condition 3) Absolute maximum sum of all input circuit currents during overload condition 3) Whatever is lower VDDP3 + ΣIIN SR -0.5 - 7.0 V -10 - 10 mA -100 - 100 mA 1) Valid for cumulated for up to 2.8h and pulse forms following a power supply switch on phase, where the rise and fall times are releated to the system capacities and coils. 2) Voltages below VINmin have no Impact to the device reliabiltiy as Long as the times and currents defined in section Pin Reliability in Overload for the affected pad(s) are not violated. 3) This parameter is an Absolute Maximum Rating. Exposure to Absolute Maximum Ratings for extended periods of time may damage the device. Data Sheet 3-317 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationPin Reliability in Overload 3.3 Pin Reliability in Overload When receiving signals from higher voltage devices, low-voltage devices experience overload currents and voltages that go beyond their own IO power supplies specification. The following table defines overload conditions that will not cause any negative reliability impact if all the following conditions are met: • full operation life-time (24500 h) is not exceeded • Operating Conditions are met for – pad supply levels – temperature If a pin current is out of the Operating Conditions but within the overload parameters, then the parameters functionality of this pin as stated in the Operating Conditions can no longer be guaranteed. Operation is still possible in most cases but with relaxed parameters. Note: An overload condition on one or more pins does not require a reset. Table 3-2 Overload Parameters Parameter Symbol Input current on any digital pin IIN during overload condition Values Min. Typ. Max. -5 - 5 -15 1) - 15 1) Unit Note / Test Condition mA except LVDS pins mA except LVDS pins; limited to max. 20 pulses with 1ms pulse length Input current on LVDS pin during overload condition IINLVDS -3 - 3 mA Absolute maximum sum of all input circuit currents during overload condition IING -50 - 50 mA Input current on analog input pin during overload condition IINANA -3 - 3 mA -5 - 5 mA Absolute sum of all ADC inputs IINSCA during overload condition -20 - 20 mA Absolute maximum sum of all input circuit currents during overload condition -100 - 100 mA Signal voltage over/undershoot VOUS at GPIOs VSS - 2 - VEXT/FLEX V limited to 60h over lifetime; Valid for LP, MP, MP+, and MPR pads Inactive device pin current during overload condtion 2) IID -1 - 1 mA All power supply voltages VDDx = 0 Sum of all inactive device pin currents 2) IIDS -100 - 100 mA Data Sheet ΣIINS +2 3-318 limited to 60h over lifetime V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationPin Reliability in Overload Table 3-2 Overload Parameters (cont’d) Parameter Overload coupling factor for digital inputs, negative 3) Data Sheet Symbol KOVDN CC Values Unit Note / Test Condition Min. Typ. Max. - - 4*10-3 Overload injected on GPIO non LVDS pad and affecting neighbor A2 pads of P24.x and P25.x; -2mA < IIN < 0mA - 2*10-4 - Overload injected on GPIO non LVDS pad and affecting neighbor LP and A2 (exept P24.x and P25.x) pads; -2mA < IIN < 0mA - - 1*10-2 Overload injected on GPIO non LVDS pad and affecting neighbor LP and A2 pads (exept P25.2 and P25.4); 5mA < IIN < -2mA - - 6*10-4 Overload injected on GPIO non LVDS pad and affecting neighbor LP and A2 pads; -2mA < IIN < 0mA - - 1.7*10-3 Overload injected on GPIO non LVDS pad and affecting neighbor MP, MP+, and MPR pads; -2mA < IIN < 0mA - - 2*10-2 Overload injected on GPIO non LVDS pad and affecting neighbor MP, MP+, and MPR pads; -5mA < IIN < 2mA - - 1.5*10-2 Overload injected on GPIO non LVDS pad and affecting neighbor pads P25.2 and P25.4; -5mA < IIN < -2mA - - 0.3 Overload injected on LVDS pad and affecting neighbor LVDS pads - - 0.93 coupling between pads 21.0, 21.1,21.2 and V 1.0 2017-03 21.3 3-319 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationPin Reliability in Overload Table 3-2 Overload Parameters (cont’d) Parameter Symbol Overload coupling factor for digital inputs, positive 3) Overload coupling factor for analog inputs, negative Overload coupling factor for analog inputs, positive 1) 2) 3) 4) KOVDP CC KOVAN CC KOVAP CC Values Unit Note / Test Condition Min. Typ. Max. - - 1*10-5 Overload injected on GPIO non LVDS pad and affecting neighbor GPIO non LVDS pads - - 1.6*10-4 Overload injected on GPIO pad and affecting neighbor P32.0 pad - - 1*10-4 Overload injected on GPIO pad and affecting neighbor P32.4 and P33.12 pad - - 5*10-4 Overload injected on LVDS pad and affecting neighbor LVDS pads - - 6*10-4 4) Analog Inputs overlaid with class LP pads or pull down diagnostics; -1mA < IIN < 0mA - - 1*10-2 Analog Inputs overlaid with class LP pads or pull down diagnostics; -5mA < IIN < -1mA - - 1*10-4 else; -5mA < IIN < 0mA - -5 - 1*10 5mA < IIN < 0mA Reduced VADC / DSADC result accuracy and / or GPIO input levels (VIL and VIH) can differ from specified parameters. Limitations for time and supply levels specified in this section are not valid for this parameter. Overload is measured as increase of pad leakage caused by injection on neighbor pad. For analogue inputs overlaid with DSADC function the VCM holdbuffer shall be enabled, in case DSADCs are enabled. Note: DSADC input pins count as analog pins as they are overlaid with VADC pins. Table 3-3 PN-Junction Characteristics for positive Overload Pad Type IIN = 3 mA IIN = 5 mA F / A2 UIN = VDDP3 + 0.5 V UIN = VDDP3 + 0.6 V LP / MP / MP+ UIN = VEXT / FLEX + 0.75 V UIN = VEXT / FLEX + 0.8 V LVDSM UIN = VEXT + 0.75 V - LVDSH UIN = VDDP3 + 0.5 V - D UIN = VDDM + 0.75 V - Data Sheet 3-320 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationPin Reliability in Overload Table 3-4 PN-Junction Characteristics for negative Overload Pad Type IIN = -3 mA IIN = -5 mA F / A2 UIN = VSS - 0.5 V UIN = VSS - 0.6 V LP / MP / MP+ UIN = VSS - 0.75 V UIN = VSS - 0.8 V LVDSM UIN = VSS - 0.75 V - LVDSH UIN = VSS - 0.5 V - D UIN = VSS - 0.75 V - Data Sheet 3-321 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationOperating Conditions 3.4 Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the TC290 / TC297 / TC298 / TC299. All parameters specified in the following tables refer to these operating conditions, unless otherwise noticed. Digital supply voltages applied to the TC290 / TC297 / TC298 / TC299 must be static regulated voltages. All parameters specified in the following tables refer to these operating conditions (see table below), unless otherwise noticed in the Note / Test Condition column. Table 3-5 Operating Conditions Parameter SRI frequency Max System Frequency CPU0 Frequency CPU1 Frequency CPU2 Frequency Symbol fSRI SR fMAX SR fCPU0 SR fCPU1 SR fCPU2 SR Values Min. Typ. Max. - - 270 - - 300 - - 270 1) 1) Unit Note / Test Condition MHz 1.17V < VDD < 1.43V MHz 1.235V < VDD < 1.43V MHz 1.17V < VDD < 1.43V MHz 1.235V < VDD < 1.43V - - 300 - - 270 MHz 1.17V < VDD < 1.43V - - 300 1) MHz 1.235V < VDD < 1.43V - - 270 MHz 1.17V < VDD < 1.43V MHz 1.235V < VDD < 1.43V MHz 1.17V < VDD < 1.43V MHz 1.235V < VDD < 1.43V - - 300 - - 270 - - 300 1) 1) PLL output frequency fPLL SR 20 - 300 MHz PLL_ERAY output frequency fPLLERAY SR 20 - 400 MHz SPB frequency fSPB SR - - 90 MHz 1.17V < VDD < 1.43V - - 100 1) MHz 1.235V < VDD < 1.43V fASCLINF SR - - 270 MHz 1.17V < VDD < 1.43V MHz 1.235V < VDD < 1.43V MHz 1.17V < VDD < 1.43V MHz 1.235V < VDD < 1.43V MHz 1.17V < VDD < 1.43V MHz 1.235V < VDD < 1.43V ASCLIN fast frequency ASCLIN slow frequency Baud2 frequency Baud1 frequency FSI2 frequency FSI frequency GTM frequency EBU frequency Data Sheet - - 300 fASCLINS SR - - 90 fBAUD2 SR fBAUD1 SR fFSI2 SR fFSI SR fGTM SR fEBU SR - - 100 - - 270 1) 1) 1) - - 300 - - 90 MHz 1.17V < VDD < 1.43V - - 100 1) MHz 1.235V < VDD < 1.43V - - 270 MHz 1.17V < VDD < 1.43V MHz 1.235V < VDD < 1.43V MHz 1.17V < VDD < 1.43V MHz 1.235V < VDD < 1.43V MHz 1.17V < VDD < 1.43V MHz 1.235V < VDD < 1.43V - - 300 - - 90 - - 100 - - 90 1) 1) 1) - - 100 - - 180 MHz 1.17V < VDD < 1.43V - - 200 MHz 1.235V < VDD < 1.43V 3-322 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationOperating Conditions Table 3-5 Operating Conditions (cont’d) Parameter STM frequency Symbol fSTM SR Values Min. Typ. Max. - - 90 - - 100 1) Unit Note / Test Condition MHz 1.17V < VDD < 1.43V MHz 1.235V < VDD < 1.43V ERAY frequency fERAY SR - - 80 MHz BBB frequency fBBB SR - - 150 MHz MultiCAN frequency fCAN SR - - 100 MHz Absolute sum of short circuit currents of the device ΣISC_D SR - - 100 mA Ambient Temperature TA SR -40 - 125 °C valid for all SAK products -40 - 150 °C valid for all SAL products -40 - 170 °C valid for all SAL products without package -40 - 150 °C valid for all SAK products -40 - 170 °C valid for all SAL products Only required if externally supplied Junction Temperature TJ SR Core Supply Voltage 2) VDD SR 1.17 1.3 1.43 3) V ADC analog supply voltage VDDM SR 2.97 5.0 5.5 4) V Digital external supply voltage for LP, MP, MP+ and LVDSM pads and EVR 5) VEXT SR 2.97 - 4.5 V 3.3V pad parameters are valid 4.5 5.0 5.5 4) V 5V pad parameters are valid Digital supply voltage for Flex port VFLEX SR 2.97 - 4.5 V 3.3V pad parameters are valid 4.5 5.0 5.5 4) V 5V pad parameters are valid Digital supply voltage for LVDSH and A2 pads 6) VDDP3 SR 2.97 3.3 3.63 7) V 3.3V pad parameters are valid; only required if externally supplied Flash supply voltage 3.3V 2) VDDFL3 SR 2.97 3.3 3.63 V Only required if externally supplied Digital ground voltage VSS SR 0 - - V Analog ground voltage for VDDM VSSM CC -0.1 0 0.1 V Voltage to ensure defined pad states 8) 0.72 - - V A2 and LVDSH 1.4 - - V LP, MP, MP+, MPR and LVDSM Data Sheet VDDPPA CC 3-323 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationOperating Conditions Table 3-5 Operating Conditions (cont’d) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition 3.3V pad parameters are valid; only required if externally supplied Digital supply voltage for EBU VEBU SR 2.97 3.3 3.63 V Digital external supply voltage for EVR and during Standby mode VEVRSB SR 2.97 - 5.5 V Digital supply voltage for EBU Flex port VFLEXE SR 2.97 3.3 4.5 V 3.3V pad parameters are valid 4.5 5.0 5.5 V 5V pad parameters are valid 1) VDD = 1.33V +- 7.5% (with increased nominal VDD) voltage by +2.5%. 2) No external inductive load permissible if EVR is used. All VDD pins shall be connected together externally on the PCB. 3) Voltage overshoot to 1.69V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and leakage is increased. 4) Voltage overshoot to 6.5V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and leakage is increased. 5) All VEXT pins shall be connected together externally on the PCB. 6) All VDDP3 pins shall be connected together externally on the PCB. 7) Voltage overshoot to 4.29V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and leakage is increased. 8) This parameter is valid under the assumption the PORST signal is constantly at low level during the power-up/power-down of VDDP3. Data Sheet 3-324 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical Specification5 V / 3.3 V switchable Pads 3.5 5 V / 3.3 V switchable Pads Pad classes LP, MP and MP+ support both Automotive Level (AL) or TTL level (TTL) operation. Parameters are defined for AL operation and degrade in TTL operation. Table 3-6 Standard_Pads Parameter Symbol Values Unit Min. Typ. Max. Note / Test Condition Pin capacitance (digital inputs/outputs) CIO CC - 6 10 pF Spike filter always blocked pulse duration tSF1 CC - - 80 ns PORST only Spike filter pass-through pulse tSF2 CC duration 220 - - ns PORST only PORST pad output current 1) 11 - - mA VEXT = 3.0V; VPORST = 0.9V; TJ = 165°C 13 - - mA IPORST CC VEXT = 4.5V; VPORST = 1.0V 1) Pull-down with IPORST relevant is always activated when a primary supply monitor detects a violation. Table 3-7 Class LP 5V Parameter Symbol Input frequency Input Hysteresis for LP pad fIN SR 1) Values Unit Note / Test Condition Min. Typ. Max. - - 75 MHz Hysteresis active - - 150 MHz Hysteresis inactive - - V AL - - V TTL -150 - 150 nA (0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX) -350 - 350 nA else -4900 - 4900 nA (0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX) -9400 - 9400 nA (0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX); for TJ > 150°C -5800 - 5800 nA else -12000 - 12000 nA else; for TJ > 150°C |30| - - µA VIHmin; AL |43| - - µA VIHmin; TTL - - |107| µA VILmax; AL and TTL HYSLP CC 0.09 * VEXT/FLEX 0.075 * VEXT/FLEX Input Leakage current for LP pad IOZLP CC Input leakage current for P32.0 IOZP320 CC Pull-up current for LP pad Data Sheet IPUHLP CC 3-325 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical Specification5 V / 3.3 V switchable Pads Table 3-7 Class LP 5V (cont’d) Parameter Symbol Pull-down current for LP pad On-Resistance for LP pad, weak driver 2) On-Resistance for LP pad, medium driver 2) Rise / fall time for LP pad 3) IPDLLP CC RDSONLPW Values Unit Note / Test Condition Min. Typ. Max. - - |100| µA VIHmin; AL and TTL |46| - - µA VILmax; AL |21| - - µA VILmax; TTL 200 620 1040 Ohm CC RDSONLPM 50 155 260 Ohm PMOS/NMOS ; IOH=2mA; IOL=2mA - - 95+2.1 * ns CL≤50pF; pin out driver=weak CC tLP CC CL - - 200+2.9 * ns ( CL - 50 ) CL≥50pF; CL≤200pF; 25+0.5 * CL≤50pF; pin out driver=medium ns CL Input high voltage for LP pad Input low voltage for LP pad VIHLP SR VILLP SR PMOS/NMOS ; IOH=0.5mA; IOL=0.5mA - pin out driver=weak 50+0.75 * ns ( CL - 50 ) CL≥50pF; CL≤200pF; (0.73*VEX T/FLEX)0.25 - V Hysteresis active, AL 2.03 4) - - V Hysteresis active, TTL - - (0.52*VEX V T/FLEX)0.25 Hysteresis active, AL - - 0.8 5) V Hysteresis active, TTL Hysteresis inactive; not available for P14.2, P14.4, P15.1, P15.10 and P15.11 pin out driver=medium Input low / high voltage for LP pad VILHLP CC 1.85 - 3.0 V Pad set-up time for LP pad tSET_LP CC - - 100 ns -150 - 1030 nA (0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX); TJ > 150°C -150 - 340 nA (0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX); TJ = 150°C -420 - 1100 nA else; TJ > 150°C -350 - 380 nA else; TJ = 150°C - |105| µA VIHmin; AL and TTL |41| - - µA VILmax; AL |16| - - µA VILmax; TTL Input leakage current for P02.1 IOZ021 CC Pull down current for P32_0 pin IPDLP320 CC - Data Sheet 3-326 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical Specification5 V / 3.3 V switchable Pads Table 3-7 Class LP 5V (cont’d) Parameter Symbol Values Min. Unit Note / Test Condition Typ. Max. IPUHP320 CC |25| - - µA VIHmin; AL |38| - - µA VIHmin; TTL - - |112| µA VILmax; AL and TTL Short Circuit current for LP pad ISC SR -10 - 10 mA absolute max value (PSI5) Deviation of symmetry for rising SYM CC and falling edges - - 20 % Pull Up Current for P32_0 pin 6) 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged. 3) Rise / fall times are defined 10% - 90% of VEXT/FLEX. 4) VIHx = 0.27 * VEXT/FLEX + 0.545V 5) VILx = 0.17 * VEXT/FLEX 6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation. Table 3-8 Class LP 3.3V Parameter Symbol Input frequency Input Hysteresis for LP pad Input Leakage current for LP pad Pull-down current for LP pad On-Resistance for LP pad, weak driver 2) Data Sheet Note / Test Condition Typ. Max. - - 50 MHz Hysteresis active - - 100 MHz Hysteresis inactive HYSLP CC 0.05 * VEXT/FLEX - - V AL and TTL IOZLP CC -150 - 150 nA (0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX) -350 - 350 nA else -4900 - 4900 nA (0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX) -9400 - 9400 nA (0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX); for TJ > 150 °C -5800 - 5900 nA else -12000 - 12000 nA else; for TJ > 150°C |17| - - µA VIHmin; AL |19| - - µA VIHmin; TTL - - |75| µA VILmax; AL and TTL - - |75| µA VIHmin; AL and TTL |22| - - µA VILmax; AL |11| - - µA VILmax; TTL 250 875 1500 Ohm Input leakage current for P32.0 IOZP320 CC Pull-up current for LP pad Unit Min. fIN SR 1) Values IPUHLP CC IPDLLP CC RDSONLPW CC ; NMOS/PMOS ; IOH=0.25mA; IOL=0.25mA 3-327 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical Specification5 V / 3.3 V switchable Pads Table 3-8 Class LP 3.3V (cont’d) Parameter Symbol On-Resistance for LP pad, medium driver 2) CC Rise / fall time for LP pad 3) tLP CC RDSONLPM Values Unit Min. Typ. Max. 70 235 400 Ohm - Input low voltage for LP pad VIHLP SR VILLP SR ; NMOS/PMOS ; IOH=1mA; IOL=1mA - 150+3.4 * ns CL Input high voltage for LP pad Note / Test Condition - 320+4.5 * ns ( CL - 50 ) CL≤50pF; pin out driver=weak CL≥50pF; CL≤200pF; pin out driver=weak - - 30+0.8*C ns L CL≤50pF; pin out driver=medium - - 70+1.1 * ( ns CL - 50 ) CL≥50pF; CL≤200pF; pin out driver=medium (0.73*VEX T/FLEX)0.25 - V Hysteresis active, AL 1.6 4) - - V Hysteresis active, TTL - - (0.52*VEX V T/FLEX)0.25 Hysteresis active, AL - - 0.5 5) V Hysteresis active, TTL Hysteresis inactive; not available for P14.2, P14.4, P15.1, P15.10 and P15.11 Input low / high voltage for LP pad VILHLP CC 1.1 - 1.9 V Pad set-up time for LP pad tSET_LP CC - - 100 ns -150 - 920 nA (0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX); TJ > 150°C -150 - 330 nA (0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX); TJ = 150°C -360 - 1000 nA else; TJ > 150°C -350 - 375 nA else; TJ = 150°C - |80| µA VIHmin; AL and TTL |17| - - µA VILmax; AL |6| - - µA VILmax; TTL IPUHP320 CC |12| - - µA VIHmin; AL |14| - - µA VIHmin; TTL - - |80| µA VILmax; AL and TTL Short Circuit current for LP pad ISC SR -10 - 10 mA absolute max value (PSI5) Deviation of symmetry for rising SYM CC and falling edges - - 20 % Input leakage current for P02.1 IOZ021 CC Pull down current for P32_0 pin IPDLP320 CC - Pull Up Current for P32_0 pin 6) Data Sheet 3-328 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical Specification5 V / 3.3 V switchable Pads 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged. 3) Rise / fall times are defined 10% - 90% of VEXT/FLEX. 4) VIHx = 0.27 * VEXT/FLEX + 0.545V 5) VILx = 0.17 * VEXT/FLEX 6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation. Table 3-9 Class MP 5V Parameter Symbol Input frequency Input Hysteresis for MP pad fIN SR 1) Values Unit Note / Test Condition Min. Typ. Max. - - 75 MHz Hysteresis active - - 150 MHz Hysteresis inactive - - V AL - - V TTL -500 - 500 nA (0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX) -1000 - 1000 nA else |30| - - µA VIHmin; AL |43| - - µA VIHmin; TTL - - |107| µA VILmax; AL and TTL - - |100| µA VIHmin; AL and TTL |46| - - µA VILmax; AL |21| - - µA VILmax; TTL 200 620 1040 Ohm PMOS/NMOS ; IOH=0.5mA; IOL=0.5mA 50 155 260 Ohm HYSMP CC 0.09 * VEXT/FLEX 0.075 * VEXT/FLEX Input Leakage current for MP pad Pull-up current for MP pad Pull-down current for MP pad IOZMP CC IPUHMP CC IPDLMP CC On-Resistance for MP pad, weak driver 2) RDSONMPW On-Resistance for MP pad, medium driver 2) RDSONMPM On-Resistance for MP pad, strong driver 2) Data Sheet CC CC RDSONMPS PMOS/NMOS ; IOH=2mA; IOL=2mA 20 75 CC 130 Ohm PMOS/NMOS ; IOH=8mA; IOL=8mA 3-329 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical Specification5 V / 3.3 V switchable Pads Table 3-9 Class MP 5V (cont’d) Parameter Rise / fall time for MP pad Symbol 3) tMP CC Values Unit Note / Test Condition Min. Typ. Max. - - 95+2.1*C ns L CL≤50pF; pin out driver=weak - - 200+2.9*( ns CL-50) CL≥50pF; CL≤200pF; pin out driver=weak - - 25+0.5*C ns CL≤50pF; pin out L driver=medium - - 50 + 0.75 ns * ( CL - 50 ) CL≥50pF; CL≤200pF; pin out driver=medium - - 17.5+0.25 ns *CL CL≤50pF; edge=medium ; pin out driver=strong - - 30+0.3*( CL-50) ns CL≥50pF; CL≤200pF; edge=medium ; pin out driver=strong - - 7+0.2*CL ns CL≤50pF; edge=sharp ; pin out driver=strong - - 17+0.3*( CL-50) ns CL≥50pF; CL≤200pF; edge=sharp ; pin out driver=strong (0.73*VEX T/FLEX)0.25 - V Hysteresis active, AL 2.03 4) - - V Hysteresis active, TTL - - (0.52*VEX V T/FLEX)0.25 Hysteresis active, AL - - 0.8 5) V Hysteresis active, TTL 1.85 - 3.0 V Hysteresis inactive - - 100 ns Short Circuit current for MP pad ISC SR -10 - 10 mA Deviation of symmetry for rising SYM CC and falling edges - - 20 % Input high voltage for MP pad Input low voltage for MP pad VIHMP SR VILMP SR Input low / high voltage for MP VILHMP CC pad Pad set-up time for MP pad tSET_MP CC 6) absolute max value (PSI5) 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged. 3) Rise / fall times are defined 10% - 90% of VEXT/FLEX. 4) VIHx = 0.27 * VEXT/FLEX + 0.545V 5) VILx = 0.17 * VEXT/FLEX 6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation. Data Sheet 3-330 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical Specification5 V / 3.3 V switchable Pads Table 3-10 Class MP 3.3V Parameter Symbol Input frequency Input Hysteresis for MP pad Input Leakage current for MP pad Pull-up current for MP pad Pull-down current for MP pad Unit Note / Test Condition Min. Typ. Max. - - 50 MHz Hysteresis active - - 100 MHz Hysteresis inactive HYSMP CC 0.05 * VEXT/FLEX - - V AL and TTL IOZMP CC -500 - 500 nA (0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX) -1000 - 1000 nA else |17| - - µA VIHmin; AL |19| - - µA VIHmin; TTL - - |75| µA VILmax; AL and TTL - - |75| µA VIHmin; AL and TTL |22| - - µA VILmax; AL |11| - - µA VILmax; TTL 250 875 1500 Ohm fIN SR 1) Values IPUHMP CC IPDLMP CC On-Resistance for MP pad, weak driver 2) RDSONMPW On-Resistance for MP pad, medium driver 2) RDSONMPM CC 70 235 400 Ohm 20 110 200 Ohm CC On-Resistance for MP pad, strong driver 2) CC Rise / fall time for MP pad 3) tMP CC RDSONMPS ; NMOS/PMOS ; IOH=1mA; IOL=1mA PMOS/NMOS ; IOH=4mA; IOL=4mA - - 150+3.4* CL CL≤50pF; pin out driver=weak ns - - 320+4.5*( ns CL-50) CL≥50pF; CL≤200pF; pin out driver=weak - - 30+0.8*C ns CL≤50pF; pin out driver=medium - - 70+1.1*( CL-50) L Data Sheet ; NMOS/PMOS ; IOH=0.25mA; IOL=0.25mA ns CL≥50pF; CL≤200pF; pin out driver=medium - - 32.5+0.35 ns *CL CL≤50pF; edge=medium ; pin out driver=strong - - 50+0.45*( ns CL-50) CL≥50pF; CL≤200pF; edge=medium ; pin out driver=strong - - 14.5+0.35 ns *CL CL≤50pF; edge=sharp ; pin out driver=strong - - 32+0.5*( CL-50) CL≥50pF; CL≤200pF; 3-331 ns edge=sharp ; pin out driver=strong V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical Specification5 V / 3.3 V switchable Pads Table 3-10 Class MP 3.3V (cont’d) Parameter Symbol Values Min. Input high voltage for MP pad Note / Test Condition Max. (0.73*VEX T/FLEX)0.25 - V Hysteresis active, AL 1.6 4) - - V Hysteresis active, TTL - - (0.52*VEX V T/FLEX)0.25 Hysteresis active, AL - - 0.5 5) V Hysteresis active, TTL Input low / high voltage for MP VILHMP CC pad 1.1 - 1.9 V Hysteresis inactive Pad set-up time for MP pad - - 100 ns Short Circuit current for MP pad ISC SR -10 - 10 mA Deviation of symmetry for rising SYM CC and falling edges - - 20 % Input low voltage for MP pad VIHMP SR Typ. Unit VILMP SR tSET_MP CC 6) absolute max value (PSI5) 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged. 3) Rise / fall times are defined 10% - 90% of VEXT/FLEX. 4) VIHx = 0.27 * VEXT/FLEX + 0.545V 5) VILx = 0.17 * VEXT/FLEX 6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation. Table 3-11 Class MP+ 5V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. - - 75 MHz Hysteresis active - - 150 MHz Hysteresis inactive HYSMPP 0.09 * - - V AL CC VEXT/FLEX - - V TTL -750 - 750 nA (0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX) -1500 - 1500 nA else IPUHMPP CC |30| - - µA VIHmin; AL |43| - - µA VIHmin; TTL - - |107| µA VILmax; AL and TTL Pull-down current for MP+ pad IPDLMPP CC - - |100| µA VIHmin; AL and TTL |46| - - µA VILmax; AL |21| - - µA VILmax; TTL Input frequency Input hysteresis for MP+ pad fIN SR 1) 0.075 * VEXT/FLEX Input leakage current for MP+ pad Pull-up current for MP+ pad Data Sheet IOZMPP CC 3-332 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical Specification5 V / 3.3 V switchable Pads Table 3-11 Class MP+ 5V (cont’d) Parameter Symbol On-resistance for MP+ pad, weak driver 2) RDSONMPPW RDSONMPPM On-resistance for MP+ pad, strong driver 2) RDSONMPPS Rise/fall time for MP+ pad Unit Min. Typ. Max. 200 620 1040 Ohm CC On-resistance for MP+ pad, medium driver 2) 3) Values PMOS/NMOS ; IOH=0.5mA; IOL=0.5mA 50 155 260 Ohm CC PMOS/NMOS ; IOH=2mA; IOL=2mA 20 55 90 Ohm - - 95+2.1*C ns L CL≤50pF; pin out driver=weak - - 200+2.9*( ns CL-50) CL≥50pF; CL≤200pF; pin out driver=weak - - 25+0.5*C ns L CL≤50pF; pin out driver=medium CC tMPP CC Note / Test Condition PMOS/NMOS ; IOH=8mA; IOL=8mA - - 50+0.75*( ns CL-50) CL≥50pF; CL≤200pF; pin out driver=medium - - 9+0.16*C ns CL≤50pF; L edge=medium ; pin out driver=strong - - 17+0.2*( CL-50) ns CL≥50pF; CL≤200pF; edge=medium ; pin out driver=strong - - 4+0.16*C ns CL≤50pF; edge=sharp ; pin out driver=strong L - - 12+0.21*( ns CL-50) CL≥50pF; CL≤200pF; edge=sharp ; pin out driver=strong - - 5 ns from 0.8V to 2.0V (RMII) ; CL=25pF; edge=sharp ; pin out driver=strong - - 4.5 ns CL=15pF; edge=sharp ; pin out driver=strong Input high voltage for MP+ pad VIHMPP SR Input low voltage for MP+ pad VILMPP SR (0.73*VEX T/FLEX)0.25 - V Hysteresis active, AL 2.03 4) - - V Hysteresis active, TTL - - (0.52*VEX V T/FLEX)0.25 Hysteresis active, AL - - 0.8 5) V Hysteresis active, TTL - 3.0 V Hysteresis inactive - 100 ns Input low / high voltage for MP+ VILHMPP CC 1.85 pad Pad set-up time for MP+ pad Data Sheet tSET_MPP CC - 3-333 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical Specification5 V / 3.3 V switchable Pads Table 3-11 Class MP+ 5V (cont’d) Parameter Symbol Short circuit current for MP+ pad 6) ISCMPP SR Deviation of symmetry for rising SYM CC and falling edges Values Unit Note / Test Condition absolute max value (PSI5) Min. Typ. Max. -10 - 10 mA - - 20 % 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged. 3) Rise / fall times are defined 10% - 90% of VEXT/FLEX. 4) VIHx = 0.27 * VEXT/FLEX + 0.545V 5) VILx = 0.17 * VEXT/FLEX 6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation. Table 3-12 Class MP+ 3.3V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. - - 50 MHz Hysteresis active - - 100 MHz Hysteresis inactive HYSMPP 0.05 * - - V AL and TTL CC VEXT/FLEX IOZMPP CC -750 - 750 nA (0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX) -1500 - 1500 nA else IPUHMPP CC |17| - - µA VIHmin; AL |19| - - µA VIHmin; TTL - - |75| µA VILmax; AL and TTL Pull-down current for MP+ pad IPDLMPP CC - - |75| µA VIHmin; AL and TTL |22| - - µA VILmax; AL |11| - - µA VILmax; TTL 250 875 1500 Ohm Input frequency Input hysteresis for MP+ pad fIN SR 1) Input leakage current for MP+ pad Pull-up current for MP+ pad On-resistance for MP+ pad, weak driver 2) RDSONMPPW CC On-resistance for MP+ pad, medium driver 2) RDSONMPPM On-resistance for MP+ pad, strong driver 2) RDSONMPPS Data Sheet ; NMOS/PMOS ; IOH=0.25mA; IOL=0.25mA 70 235 400 Ohm CC ; NMOS/PMOS ; IOH=1mA; IOL=1mA 20 75 CC 130 Ohm PMOS/NMOS ; IOH=4mA; IOL=4mA 3-334 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical Specification5 V / 3.3 V switchable Pads Table 3-12 Class MP+ 3.3V (cont’d) Parameter Rise/fall time for MP+ pad Symbol 3) tMPP CC Values Unit Note / Test Condition ns CL CL≤50pF; pin out driver=weak Min. Typ. Max. - - 150+3.4* - - 320+4.5*( ns CL-50) CL≥50pF; CL≤200pF; pin out driver=weak - - 30+0.8*C ns CL≤50pF; pin out L driver=medium - - 70+1.1*( CL-50) ns CL≥50pF; CL≤200pF; pin out driver=medium - - 20+0.2*C ns CL≤50pF; edge=medium ; pin out driver=strong L - - 30+0.3*( CL-50) ns CL≥50pF; CL≤200pF; edge=medium ; pin out driver=strong - - 13+0.2*C ns CL≤50pF; edge=sharp L ; pin out driver=strong - - 7.65 ns CL = 15pF; VEXT/FLEX = 3.135V; V = 0V to 2.0V; edge=sharp ; pin out driver=strong - - 5.42 ns CL = 15pF; VEXT/FLEX = 3.135V; V = 3.135V to 0.8V; edge=sharp ; pin out driver=strong - - 7.36 ns CL = 15pF; VEXT/FLEX = 3.201V; V = 0V to 2.0V; edge=sharp ; pin out driver=strong - - 5.32 ns CL = 15pF; VEXT/FLEX = 3.201V; V = 3.201V to 0.8V; edge=sharp ; pin out driver=strong - - 5.9 ns CL = 15pF; VEXT/FLEX = 3.63V; V = 0V to 2.0V; edge=sharp ; pin out driver=strong - - 4.8 ns CL = 15pF; VEXT/FLEX = 3.63V; V = 3.63V to 0.8V; edge=sharp ; pin out driver=strong - - 23+0.3*( CL-50) ns CL≥50pF; CL≤200pF; edge=sharp ; pin out driver=strong - - 5 ns from 0.8V to 2.0V (RMII) ; CL=25pF; V 1.0 2017-03 edge=sharp ; pin out driver=strong 4.5 ns from 0.2 * VEXT/FLEX to Data Sheet 3-335 - - TC290 / TC297 / TC298 / TC299 BC-Step Electrical Specification5 V / 3.3 V switchable Pads Table 3-12 Class MP+ 3.3V (cont’d) Parameter Symbol Values Min. Input high voltage for MP+ pad VIHMPP SR Typ. Unit Note / Test Condition Max. (0.73*VEX T/FLEX)0.25 - V Hysteresis active, AL 1.6 4) - - V Hysteresis active, TTL - - (0.52*VEX V T/FLEX)0.25 Hysteresis active, AL - - 0.5 5) V Hysteresis active, TTL Input low / high voltage for MP+ VILHMPP CC 1.1 pad - 1.9 V Hysteresis inactive Pad set-up time for MP+ pad tSET_MPP CC - - 100 ns Short circuit current for MP+ pad 6) ISCMPP SR -10 - 10 mA - - 20 % Input low voltage for MP+ pad VILMPP SR Deviation of symmetry for rising SYM CC and falling edges absolute max value (PSI5) 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged. 3) Rise / fall times are defined 10% - 90% of VEXT/FLEX. 4) VIHx = 0.27 * VEXT/FLEX + 0.545V 5) VILx = 0.17 * VEXT/FLEX 6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation. Table 3-13 Class MPR 5V Parameter Input frequency Symbol Values Unit Note / Test Condition Min. Typ. Max. - - 75 MHz Hysteresis active - - 150 MHz Hysteresis inactive 0.09 * - - V AL - - V TTL -750 - 750 nA (0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX) -1500 - 1500 nA else IPUHMPR CC |30| - - µA VIHmin; AL |43| - - µA VIHmin; TTL - - |107| µA VILmax; AL and TTL IPDLMPR CC - - |100| µA VIHmin; AL and TTL |46| - - µA VILmax; AL |21| - - µA VILmax; TTL fIN SR Input Hysteresis for MPR pads HYSMPR 1) CC VEXT/FLEX 0.075* VEXT/FLEX Input leakage current class MPR Pull-up current Pull-down current Data Sheet IOZMPR CC 3-336 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical Specification5 V / 3.3 V switchable Pads Table 3-13 Class MPR 5V (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. On-resistance of the MPR pad, RDSONMPRW weak driver 2) CC 200 620 1040 On-resistance of the MPR pad, RDSONMPRM medium driver 2) CC 50 On-resistance of the MPR pad, RDSONMPRS strong driver 2) CC 20 55 90 Rise/fall time 3) - - 95+2.1*C ns L CL≤50pF; pin out driver=weak - - 200+2.9*( ns CL-50) CL≥50pF; CL≤200pF; pin out driver=weak - - 25+0.5*C ns L CL≤50pF; pin out driver=medium tMPR CC Ohm 155 260 Ohm Input low voltage, class MPR pads Input low / high voltage, class MPR pads Data Sheet VIHMPR SR VILMPR SR PMOS/NMOS ; IOH=2mA; IOL=2mA Ohm PMOS/NMOS ; IOH=8mA; IOL=8mA - - 50+0.75*( ns CL-50) CL≥50pF; CL≤200pF; pin out driver=medium - - 9+0.16*C ns CL≥0pF; CL≤50pF; L edge=medium ; pin out driver=strong - - 17+0.2*( CL-50) ns CL≥50pF; CL≤200pF; edge=medium ; pin out driver=strong - - 4+0.16*C ns CL≤50pF; edge=sharp ; pin out driver=strong L Input high voltage, class MPR pads PMOS/NMOS ; IOH=0.5mA; IOL=0.5mA - - 12+0.21*( ns CL-50) CL≥50pF; CL≤200pF; edge=sharp ; pin out driver=strong - - 5 ns from 0.8V to 2.0V (RMII) ; CL=25pF; edge=sharp ; pin out driver=strong - - 4.5 ns from 0.2 * VEXT/FLEX to 0.8 * VEXT/FLEX; CL=15pF; edge=sharp ; pin out driver=strong (0.73*VEX T/FLEX)0.25 - V Hysteresis active, AL 2.03 4) - - V Hysteresis active, TTL - - (0.52*VEX V T/FLEX)0.25 Hysteresis active, AL - - 0.8 5) V Hysteresis active, TTL - 2.3 V Hysteresis inactive VILHMPR SR 1.2 3-337 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical Specification5 V / 3.3 V switchable Pads Table 3-13 Class MPR 5V (cont’d) Parameter Symbol Values Min. Pad set-up time tSET_MPR CC - Unit Typ. Max. - 100 ns Short circuit current Class MPR ISC SR -10 - 10 mA Deviation of symmetry for rising SYM CC and falling edges - - 20 % Note / Test Condition absolute max value (PSI5) 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged. 3) Rise / fall times are defined 10% - 90% of VEXT/FLEX. 4) VIHx = 0.27 * VEXT/FLEX + 0.545V 5) VILx = 0.17 * VEXT/FLEX Table 3-14 Class MPR 3.3V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. - - 50 MHz Hysteresis active - - 100 MHz Hysteresis inactive Input Hysteresis for MPR pads HYSMPR 1) CC 0.05 * - - V AL and TTL Input leakage current class MPR -750 - 750 nA (0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX) -1500 - 1500 nA else IPUHMPR CC |17| - - µA VIHmin; AL |19| - - µA VIHmin; TTL - - |75| µA VILmax; AL and TTL IPDLMPR CC - - |75| µA VIHmin; AL and TTL |22| - - µA VILmax; AL |11| - - µA VILmax; TTL On-resistance of the MPR pad, RDSONMPRW weak driver 2) CC 250 875 1500 Ohm On-resistance of the MPR pad, RDSONMPRM medium driver 2) CC 70 235 400 Ohm On-resistance of the MPR pad, RDSONMPRS strong driver 2) CC 20 75 130 Ohm Input frequency Pull-up current Pull-down current Data Sheet fIN SR IOZMPR CC VEXT/FLEX ; NMOS/PMOS ; IOH=0.25mA; IOL=0.25mA ; NMOS/PMOS ; IOH=1mA; IOL=1mA PMOS/NMOS ; IOH=4mA; IOL=4mA 3-338 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical Specification5 V / 3.3 V switchable Pads Table 3-14 Class MPR 3.3V (cont’d) Parameter Rise/fall time Symbol 3) tMPR CC Values Unit Note / Test Condition ns CL CL≤50pF; pin out driver=weak Min. Typ. Max. - - 150+3.4* - - 320+4.5*( ns CL-50) CL≥50pF; CL≤200pF; pin out driver=weak - - 30+0.8*C ns CL≤50pF; pin out L driver=medium - - 70+1.1*( CL-50) ns CL≥50pF; CL≤200pF; pin out driver=medium - - 20+0.2*C ns CL≥0pF; CL≤50pF; edge=medium ; pin out driver=strong L Input high voltage, class MPR pads Input low voltage, class MPR pads VIHMPR SR VILMPR SR - - 30+0.3*( CL-50) ns CL≥50pF; CL≤200pF; edge=medium ; pin out driver=strong - - 13+0.2*C ns CL≤50pF; edge=sharp L ; pin out driver=strong - - 23+0.3*( CL-50) ns CL≥50pF; CL≤200pF; edge=sharp ; pin out driver=strong - - 5 ns from 0.8V to 2.0V (RMII) ; CL=25pF; edge=sharp ; pin out driver=strong - - 4.5 ns from 0.2 * VEXT/FLEX to 0.8 * VEXT/FLEX; CL=15pF; edge=sharp ; pin out driver=strong (0.73*VEX T/FLEX)0.25 - V Hysteresis active, AL 1.6 4) - - V Hysteresis active, TTL - - (0.52*VEX V T/FLEX)0.25 Hysteresis active, AL - - 0.5 5) V Hysteresis active, TTL Hysteresis inactive Input low / high voltage, class MPR pads VILHMPR SR 0.8 - 1.7 V Pad set-up time tSET_MPR CC - - 100 ns - 10 mA Short circuit current Class MPR ISC SR -10 absolute max value (PSI5) 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged. Data Sheet 3-339 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical Specification5 V / 3.3 V switchable Pads 3) Rise / fall times are defined 10% - 90% of VEXT/FLEX. 4) VIHx = 0.27 * VEXT/FLEX + 0.545V 5) VILx = 0.17 * VEXT/FLEX Table 3-15 Class S Parameter Symbol Input frequency Input Hysteresis for S pad Pull-up current for S pad Pull-down current for S pad Unit Note / Test Condition Min. Typ. Max. - - 75 MHz Hysteresis active - - 150 MHz Hysteresis inactive HYSS CC 0.3 - - V IPUHS CC |30| - - µA VIHmin - - |107| µA VILmax - - |100| µA VIHmin |46| - - µA VILmax -350 - 350 nA Analog Inputs with pull down diagnostics -150 - 150 nA else - (0.73*VDD V M)-0.25 Hysteresis active fIN SR 1) Values IPDLS CC Input Leakage current Class S IOZS CC Input voltage high for S pad VIHS SR - Input voltage low for S pad VILS SR (0.52*VDD M)-0.25 - V Hysteresis active Input low threshold variation for VILSD SR S pad 2) -50 - 50 mV max. variation of 1ms; VDDM=constant Input capacitance for S pad CINS CC - - 10 pF Pad set-up time for S pad tSETS CC - - 100 ns 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 2) VILSD is implemented to ensure J2716 specification. For details of dedicated pins please see AP32286 for details. Table 3-16 Class I 5V Parameter Input frequency Input Hysteresis for I pad 1) Symbol fIN SR HYSI CC Values Unit Note / Test Condition Min. Typ. Max. - - 75 MHz Hysteresis active - - 150 MHz Hysteresis inactive 0.07 * - - V PORST pad only - - V AL - - V TTL |30| - - µA VIHmin; AL |43| - - µA VIHmin; TTL - - |107| µA VILmax; AL and TTL VEXT/FLEX 0.09 * VEXT/FLEX 0.075 * VEXT/FLEX Pull-up current for I pad Data Sheet IPUHI CC 3-340 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical Specification5 V / 3.3 V switchable Pads Table 3-16 Class I 5V (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. - - |100| µA VIHmin; AL and TTL |46| - - µA VILmax; AL |21| - - µA VILmax; TTL -150 - 150 nA (0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX) -350 - 350 nA else 2.03 2) - - V Hysteresis active, TTL (0.73*VEX T/FLEX)0.25 - V Hysteresis active; AL; not available for the PORST pad - - 0.8 3) V Hysteresis active, TTL - - (0.52*VEX V T/FLEX)0.25 Hysteresis active; AL; not available for the PORST pad Input low / high voltage for I pad VILHI CC 1.85 - 3.0 V Hysteresis inactive Pad set-up time for I pad - - 100 ns Pull-down current for I pad IPDLI CC Input Leakage Current for I pad IOZI CC Input high voltage for I pad Input low voltage for I pad VIHI SR VILI SR tSETI CC 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 2) VIHx = 0.27 * VEXT/FLEX + 0.545V 3) VILx = 0.17 * VEXT/FLEX Table 3-17 Class I 3.3V Parameter Symbol Input frequency Input Hysteresis for I pad fIN SR 1) HYSI CC Values Unit Note / Test Condition Min. Typ. Max. - - 50 MHz Hysteresis active - - 100 MHz Hysteresis inactive 0.045 * - - V PORST pad only - - V AL and TTL |17| - - µA VIHmin; AL |19| - - µA VIHmin; TTL - - |75| µA VILmax; AL and TTL - - |75| µA VIHmin; AL and TTL |22| - - µA VILmax; AL |11| - - µA VILmax; TTL -150 - 150 nA (0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX) -350 - 350 nA else VEXT/FLEX 0.05 * VEXT/FLEX Pull-up current for I pad Pull-down current for I pad IPUHI CC IPDLI CC Input Leakage Current for I pad IOZI CC Data Sheet 3-341 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical Specification5 V / 3.3 V switchable Pads Table 3-17 Class I 3.3V (cont’d) Parameter Symbol Values Min. Unit Note / Test Condition Typ. Max. - - V Hysteresis active, TTL (0.73*VEX T/FLEX)0.25 - V Hysteresis active; AL; not available for the PORST pad - - 0.5 3) V Hysteresis active, TTL - - (0.52*VEX V T/FLEX)0.25 Hysteresis active; AL; not available for the PORST pad Input low / high voltage for I pad VILHI CC 1.1 - 1.9 V Hysteresis inactive Pad set-up time for I pad - - 100 ns Input high voltage for I pad VIHI SR Input low voltage for I pad VILI SR tSETI CC 1.6 2) 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 2) VIHx = 0.27 * VEXT/FLEX + 0.545V 3) VILx = 0.17 * VEXT/FLEX Table 3-18 Class A2 Parameter Symbol Input frequency Input Hysteresis for A2 pad Unit Typ. Max. - - 160 MHz HYSA2 CC 0.1 * VDDP3 - - V TTL;else 0.06 * - - V valid for P21.6 and P21.7 -300 - 300 nA (0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX) -800 - 500 nA else - - |100| µA VIHmin |25| - - µA VILmax |23| - - µA VIHmin - - |100| µA VILmax 100 200 325 Ohm VDDP3 Input Leakage current for A2 pad Pull-up current for A2 pad Pull-down current for A2 pad IOZA2 CC IPUHA2 CC IPDLA2 CC On-Resistance for A2 pad, weak driver 2) CC On-Resistance for A2 pad, medium driver 2) CC On-Resistance for A2 pad, strong driver 2) Data Sheet Note / Test Condition Min. fIN SR 1) Values RDSONA2W RDSONA2M RDSONA2S PMOS/NMOS ; IOH=0.5mA; IOL=0.5mA 40 70 100 Ohm PMOS/NMOS ; IOH=2mA; IOL=2mA 20 35 CC 50 Ohm PMOS/NMOS ; IOH=8mA; IOL=8mA 3-342 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical Specification5 V / 3.3 V switchable Pads Table 3-18 Class A2 (cont’d) Parameter Rise/fall time for A2 pad Symbol 3) tA2 CC Values Unit Min. Typ. Max. - - 20+0.8*C ns L CL≤50pF; pin out driver=weak - - 17.5+0.85 ns *CL CL≥50pF; CL≤200pF; pin out driver=weak - - 12+0.16* CL≤50pF; pin out ns CL driver=medium - - 11.5+0.17 ns *CL CL≥50pF; CL≤200pF; pin out driver=medium - - 6+0.06*C ns CL≤50pF; edge=medium ; pin out driver=strong L - - - - 5.5+0.07* ns CL CL≥50pF; CL≤200pF; edge=medium ; pin out driver=strong 0.0+0.12* ns CL≤50pF; edge=sharp CL ; pin out driver=strong 0.0+0.12* ns CL≥50pF; CL≤200pF; edge=sharp ; pin out driver=strong CL Input high voltage for A2 pad VIHA2 SR 2.04 4) - - V TTL;valid for all A2 pads except TMS/DAP1, TRST, and TCK/DAP0 0.7 * - - V valid for TMS/DAP1, TRST, and TCK/DAP0 - - 0.8 5) V TTL;valid for all A2 pads except TMS/DAP1, TRST, and TCK/DAP0 - - 0.3 * V valid for TMS/DAP1, TRST, and TCK/DAP0 VDDP3 Input low voltage for A2 pad VILA2 SR VDDP3 Pad set-up time for A2 pad tSETA2 CC Deviation of symmetry for rising SYM CC and falling edges Note / Test Condition - - 100 ns - - 20 % 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged. 3) Rise / fall times are defined 10% - 90% of VDDP3. 4) VIHx = 0.57 * VDDP3 - 0.03V 5) VILx = 0.25 * VDDP3 + 0.058V Data Sheet 3-343 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical Specification5 V / 3.3 V switchable Pads Table 3-19 Driver Mode Selection for LP Pads PDx.2 PDx.1 PDx.0 Port Functionality Driver Setting X X 0 Speed grade 1 medium (LPm) X X 1 Speed grade 2 weak (LPw) Table 3-20 Driver Mode Selection for MP / MP+ Pads PDx.2 PDx.1 PDx.0 Port Functionality Driver Setting X 0 0 Speed grade 1 Strong sharp edge (MPss / MP+ss) X 0 1 Speed grade 2 Strong medium edge (MPsm / MP+sm) X 1 0 Speed grade 3 medium (MPm / MP+m) X 1 1 Speed grade 4 weak (MPw / MP+w) Table 3-21 Driver Mode Selection for A2 Pads PDx.2 PDx.1 PDx.0 Port Functionality Driver Setting X 0 0 Speed grade 1 Strong sharp edge X 0 1 Speed grade 2 Strong medium edge X 1 0 Speed grade 3 medium X 1 1 Speed grade 4 weak Table 3-22 Driver Mode Selection for F Pads PDx.2 PDx.1 PDx.0 Port Functionality Driver Setting X 0 0 Speed grade 1 Reduced Strong sharp edge X 0 1 Speed grade 2 Reduced Strong medium edge X 1 0 Speed grade 3 medium X 1 1 Speed grade 4 weak Data Sheet 3-344 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationHigh performance LVDS Pads (LVDSH) 3.6 High performance LVDS Pads (LVDSH) This LVDS pad type is used for the high speed chip to chip communication inferface of the new TC290 / TC297 / TC298 / TC299. It compose out of a LVDSH pad and a Class F pad. This pad combination is always supplied by the 3.3V supply rail. Table 3-23 Class F Parameter Symbol Values Unit Min. Typ. Max. Note / Test Condition Input frequency fIN SR - - 75 MHz Input Hysteresis for F pad 1) HYSF CC 0.1 * - - V TTL -1000 - - nA (0.1*VDDP3) < VIN < (0.9*VDDP3); valid for P21.0, P21.1, P21.2 and P21.3; TJ = 150°C - - 1000 nA (0.1*VDDP3) < VIN < (0.9*VDDP3); valid for P21.0, P21.1, P21.2 and P21.3; TJ = 150°C -1500 - 1500 nA (0.1*VDDP3) < VIN < (0.9*VDDP3); valid for P21.0, P21.1, P21.2 and P21.3; TJ = 170°C -300 - 300 nA (0.1*VDDP3) < VIN < (0.9*VDDP3); valid for P21.4 and P21.5 - - 2000 nA else; valid for P21.0, P21.1, P21.2 and P21.3; TJ = 150°C -2000 - - nA else; valid for P21.0, P21.1, P21.2 and P21.3; TJ = 150°C -3000 - 3000 nA else; valid for P21.0, P21.1, P21.2 and P21.3; TJ = 170°C -600 - 600 nA else; valid for P21.4 and P21.5 |25| - - µA VIHmin - - |100| µA VILmax - - |100| µA VIHmin |25| - - µA VILmax 100 200 325 Ohm PMOS/NMOS ; IOH=0.5mA; IOL=0.5mA VDDP3 Input Leakage Current for F pad Pull-up current for F pad IOZF CC IPUHF CC Pull-down current for class F pads IPDLF CC On resistance for F pad, weak driver 2) RDSONFW Data Sheet CC 3-345 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationHigh performance LVDS Pads (LVDSH) Table 3-23 Class F (cont’d) Parameter On resistance for F pad, medium driver 2) Symbol RDSONFM Values Unit Min. Typ. Max. 40 70 100 Ohm CC PMOS/NMOS ; IOH=2mA; IOL=2mA On resistance for F pad, strong RDSONFS CC 20 driver 2) 50 Rise/fall time for F pad 3) - trfF CC Note / Test Condition - 80 Ohm PMOS/NMOS ; IOH=4mA; IOL=4mA 20+0.8*C ns CL≤50pF; pin out L driver=weak - - 17.5+0.85 ns *CL CL≥50pF; CL≤200pF; pin out driver=weak - - 12+0.16* CL CL≤50pF; pin out driver=medium ns - - 11.5+0.17 ns *CL CL≥50pF; CL≤200pF; pin out driver=medium - - 7+0.16*C ns CL≤50pF; edge=medium ; pin out driver=reduced strong L - - 6.5+0.17* ns CL - - 4+0.16*C ns L - - 3.5+0.17* ns CL CL≥50pF; CL≤200pF; edge=meduim ; pin out driver>reduced strong CL≤50pF; edge=sharp ; pin out driver=reduced strong CL≥50pF; CL≤200pF; edge=sharp ; pin out driver=reduced strong Input high voltage for F pad VIHF SR 2.04 4) - - V TTL Input low voltage for F pad VILF SR - - 0.8 5) V TTL Pad set-up time for F pad tSETF CC - - 100 ns Deviation of symmetry for rising SYM CC and falling edges - - 20 % 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise. 2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged. 3) Rise / fall times are defined 10% - 90% of VDDP3. 4) VIHx = 0.57 * VDDP3 - 0.03V 5) VILx = 0.25 * VDDP3 + 0.058V CL = 2.5 pF for all LVDSH parameters. Data Sheet 3-346 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationHigh performance LVDS Pads (LVDSH) Table 3-24 LVDSH - IEEE standard LVDS general purpose link (GPL) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. R0 CC 40 - 140 Ohm Vcm = 1.0 V and 1.4 V trise20 CC - - 0.5 ns ZL = 100 Ohm ±5% @2 pF Fall time 1) tfall20 CC - - 0.5 ns ZL = 100 Ohm ±5% @ 2 pF Output differential voltage VOD CC 250 - 400 mV RT = 100 Ohm ±5% Output voltage high VOH CC - - 1475 mV RT = 100 Ohm ±5% (400 mV/2) + 1275 mV Output voltage low VOL CC 925 - - mV RT = 100 Ohm ±5% 1125 - 1275 mV RT = 100 Ohm ±5% 0 - 1600 mV Driver ground potential difference < 925 mV; RT = 100 Ohm ±10% 0 - 2000 mV Driver ground potential difference < 925 mV; RT = 100 Ohm ±20% Output impedance Rise time 1) Output offset (Common mode) VOS CC voltage Input voltage range VI SR Input differential threshold Vidth SR -100 - 100 mV Driver ground potential difference < 925 mV Delta output impedance dR0 SR - - 10 % Vcm = 1.0 V and 1.4 V (mismatch Pd and Pn) Change in VOS between 0 and dVOS CC 1 - - 25 mV RT = 100 Ohm ±5% Change in Vod between 0 and dVod CC 1 - - 25 mV RT = 100 Ohm ±5% Duty cycle 45 - 55 % tduty CC 1) Rise / fall times are defined for 20% - 80% of VOD Table 3-25 LVDSH - IEEE standard LVDS reduced link (REDL) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Output impedance R0 CC 40 - 140 Ohm Vcm = 1.0 V and 1.4 V Output differential voltage VOD CC 150 - 250 mV RT = 100 Ohm ±5% Output voltage high VOH CC - - 1375 mV RT = 100 Ohm ±5% Output voltage low VOL CC 1025 - - mV RT = 100 Ohm ±5% Output offset (Common mode) VOS CC voltage 1125 - 1275 mV RT = 100 Ohm ±5% 825 - 1575 mV Driver ground potential difference < 50 mV Input voltage range Data Sheet VI SR 3-347 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationHigh performance LVDS Pads (LVDSH) Table 3-25 LVDSH - IEEE standard LVDS reduced link (REDL) (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. -100 - 100 mV Driver ground potential difference < 50 mV Change in VOS between 0 and dVOS CC 1 - - 25 mV RT = 100 Ohm ±5% Change in Vod between 0 and dVod CC 1 - - 25 mV RT = 100 Ohm ±5% tduty CC 45 - 55 % tfall10 CC - - 0.5 ns ZL = 100 Ohm ±5% @ 2pF trise10 CC - - 0.5 ns ZL = 100 Ohm ±5% @ 2pF Input differential threshold Duty cycle VOD Fall time VOD Rise time 1) 1) Vidth SR 1) Rise / fall times are defined for 10% - 90% of VOD default after start-up = CMOS function P Htotal=5nH Ctotal=3.5pF Cext=2pF Rin LVDSH IN RT=100Ohm N Htotal=5nH Ctotal=3.5pF Cext=2pF LVDSH _Input _Pad _Model .vsd Figure 3-1 LVDSH pad Input model Data Sheet 3-348 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationMedium performance LVDS Pads (LVDSM) 3.7 Medium performance LVDS Pads (LVDSM) This LVDS pad type is used for the medium speed chip to chip communication inferface of the new TC290 / TC297 / TC298 / TC299. It compose out of a LVDSM pad and a MP pad. This pad combination is always supplied by the 5V or 3.3V. For the parameters of the MP pad please see Chapter 3.5. Table 3-26 LVDSM Parameter Symbol Values Unit Min. Typ. Max. Note / Test Condition Output impedance RO CC 40 100 140 Ohm Fall time tF CC - - 2.5 ns Zload = 100 Ohm; termination 100 Ohm ±1% Rise time tR CC - - 2.5 ns Zload = 100 Ohm; termination 100 Ohm ±1% tSET_LVDS - 10 13 µs Pad set-up time CC Output Differential Voltage VOD CC 250 - 400 mV termination 100 Ohm ±1% Output voltage high VOH CC - - 1475 mV termination 100 Ohm ±1% Output voltage low VOL CC 925 - - mV termination 100 Ohm ±1% Output Offset Voltage VOS CC 1125 - 1275 mV termination 100 Ohm ±1% default after start-up = CMOS function Data Sheet 3-349 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationVADC Parameters 3.8 VADC Parameters VADC parameter are valid for VDDM = 4.5 V to 5.5 V. This table also covers the parameters for Class D pads. Table 3-27 VADC Parameter Symbol Analog reference voltage 1) VAREF SR Values Min. Typ. Max. VAGND + - VDDM + 1.0 Analog reference ground VAGND SR Unit VSSM - Note / Test Condition V 0.05 - 0.05 VSSM + V 0.05 Analog input voltage range VAIN SR VAGND - VAREF V Converter reference clock fADCI SR 2 - 20 MHz Charge consumption per conversion 2) 3) QCONV CC - 50 75 pC VAIN = 5 V, charge consumed from reference pin, precharging disabled - 10 22 pC VAIN = 5 V, charge consumed from reference pin, precharging enabled Conversion time for 12-bit result tC12 CC - (16 + STC) x tADCI + 2 x Includes sample time and post calibration tVADC Conversion time for 10-bit result tC10 CC - (14 + STC) x tADCI + 2 x Includes sample time tVADC Conversion time for 8-bit result tC8 CC - (12 + STC) x tADCI + 2 x Includes sample time tVADC Conversion time for fast compare mode tCF CC - (4 + STC) x tADCI + 2 x tVADC Broken wire detection delay against VAGND 4) tBWG CC - - 120 cycles Result below 10% Broken wire detection delay against VAREF 5) tBWR CC - - 60 cycles Result above 80% Input leakage at analog inputs IOZ1 CC -350 - 350 nA Analog Inputs overlaid with class LP pads or pull down diagnostics -150 - 150 nA else LSB 12-bit resolution Total Unadjusted Error Data Sheet 1) TUE CC -4 6) - 3-350 4 Includes sample time 6) V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationVADC Parameters Table 3-27 VADC (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. EAINL CC -3 - 3 LSB 12-bit resolution EAGAIN CC -3.5 - 3.5 LSB 12-bit resolution EADNL CC -3 - 3 LSB 12-bit resolution EAOFF CC -4 - 4 LSB 12-bit resolution Total capacitance of an analog CAINT CC input - - 30 pF CAINS CC 2 4 7 pF Resistance of the analog input RAIN CC path - - 1.5 kOhm else - - 1.8 kOhm valid for analog inputs mapped to GPIOs Switched capacitance of a reference input CAREFS CC - - 30 pF RMS Noise 7) ENRMS CC - 0.5 0.8 6)8) LSB Positive reference VAREFx pin leakage IOZ2 CC -7 - 7 µA VAREFx = VAREF2; VAREF>VDDMV; TJ>150°C -4 - 4 µA VAREFx = VAREF2; VAREF>VDDMV; TJ≤150°C -2 - 3 µA VAREFx = VAREF2; VAREF≤VDDMV; TJ>150°C -1 - 1 µA VAREFx = VAREF2; VAREF≤VDDMV; TJ≤150°C -13 - 13 µA VAGNDx = VAGND2; VAGND150°C -7 - 7 µA VAGNDx = VAGND2; VAGND150°C -2.5 - 1 µA VAGNDx = VAGND2; VAREF≤VDDMV; TJ≤150°C INL Error Gain Error DNL error 1) 1) Offset Error 1) Switched capacitance of an analog input Negative reference VAGNDx pin leakage IOZ3 CC Resistance of the reference input path RAREF CC - - 1 kOhm CSD resistance 9) RCSD CC - - 28 kOhm Data Sheet 3-351 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationVADC Parameters Table 3-27 VADC (cont’d) Parameter Symbol Values Min. Resistance of the multiplexer diagnostics pull-down device RMDD CC Resistance of the multiplexer diagnostics pull-up device RMDU CC Typ. Unit Note / Test Condition Max. 25 + 1*VIN - 35 - 8*VIN kOhm 0 V ≤ VIN ≤ 2.5 V -5 + 13*VIN - 15 + 16*VIN kOhm 2.5 V ≤ VIN ≤ VDDM 45 - 6*VIN - 90 16*VIN kOhm 0 V ≥ VIN ≤ 2.5 V 40 - 4*VIN - 65 - 6*VIN kOhm Resistance of the pull-down test device 10) RPDD CC - - 0.3 kOhm CSD voltage accuracy 11) 12) dVCSD CC - - 10 % Wakeup time tWU CC - 12 µs - 2.5 V ≤ VIN ≤ VDDM 1) If the reference voltage is reduced by the factor k (k < 1), TUE,DNL,INL,Gain, and Offset errors increase also by the factor 1/k. VAREF must be decoupled with an external capacitor. 2) For QCONV = X pC and a conversion time of 1 µs a rms value of X µA results for IAREFx. 3) For the details of the mapping for a VADC group to pin VAREFx please see the User's Manual. 4) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a conversion rate higher than 1 conversion per 500 ms. 5) The broken wire detection delay against VAREF is measured in numbers of consecutive precharge cycles at a conversion rate higher than 1 conversion per 10 ms. This function is influenced by leakage current, in particular at high temperature. 6) Resulting worst case combined error is arithmetic combination of TUE and ENRMS. 7) This parameter is valid for soldered devices and requires careful analog board design. 8) Value is defined for one sigma Gauss distribution. 9) In order to avoid an additional error due to incomplete sampling, the sampling time shall be set greater than 5 * RCSD * CAINS. 10) The pull-down resistor RPDD is connected between the input pad and the analog multiplexer. The input pad itself adds another 200-Ohm series resistance, when measuring through the pin. 11) CSD: Converter Self Diagnostics, for details please consult the User's Manual. 12) Note, that in case CSD voltage is chosen to nom. 1/3 or 2/3 of VAREF voltage, the reference voltage is loaded with a current of max. VAREF / 45 kOhm. The following VADC parameter are valid for VDDM = 2.97 V to 4.5 V. This table also covers the parameters for Class D pads. Table 3-28 VADC_33V Parameter Analog reference voltage Symbol 1) VAREF SR Values Min. Typ. Max. VAGND + - VDDM + 1.0 Analog reference ground VAGND SR Unit VSSM - V 0.05 - 0.05 VSSM + V 0.05 Analog input voltage range VAIN SR VAGND - VAREF V Converter reference clock fADCI SR 2 - 20 MHz Data Sheet Note / Test Condition 3-352 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationVADC Parameters Table 3-28 VADC_33V (cont’d) Parameter Symbol Charge consumption per conversion 2) 3) QCONV CC Values Min. Typ. Max. - 35 50 Unit Note / Test Condition pC VAIN = 3.3 V, charge consumed from reference pin, precharging disabled - 8 17 pC VAIN = 3.3 V, charge consumed from reference pin, precharging enabled Conversion time for 12-bit result tC12 CC - (16 + STC) x tADCI + 2 x Includes sample time and post calibration tVADC Conversion time for 10-bit result tC10 CC - (14 + STC) x tADCI + 2 x Includes sample time tVADC Conversion time for 8-bit result tC8 CC - (12 + STC) x tADCI + 2 x Includes sample time tVADC Conversion time for fast compare mode tCF CC - (4 + STC) x tADCI + 2 x tVADC Broken wire detection delay against VAGND 4) tBWG CC - - 120 cycles Result below 10% Broken wire detection delay against VAREF 5) tBWR CC - - 60 cycles Result above 80% Input leakage at analog inputs IOZ1 CC -350 - 350 nA Analog Inputs overlaid with class LP pads or pull down diagnostics -150 - 150 nA else LSB 12-bit Resolution; TJ > 150 °C Total Unadjusted Error INL Error Gain Error 1) Data Sheet 1) TUE CC EAINL CC EAGAIN CC -12 6) Includes sample time 6) - 12 -6 6) - 6 6) LSB 12-bit Resolution; TJ ≤ 150 °C -12 - 12 LSB 12-bit Resolution; TJ > 150 °C -5 - 5 LSB 12-bit Resolution; TJ ≤ 150 °C -6 - 6 LSB 12-bit Resolution; TJ > 150 °C -5.5 - 5.5 LSB 12-bit Resolution; TJ ≤ 150 °C 3-353 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationVADC Parameters Table 3-28 VADC_33V (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. EADNL CC -4 - 4 LSB 12-bit resolution EAOFF CC -6 - 6 LSB 12-bit Resolution; TJ > 150 °C -5 - 5 LSB 12-bit Resolution; TJ ≤ 150 °C Total capacitance of an analog CAINT CC input - - 30 pF CAINS CC 2 4 7 pF Resistance of the analog input RAIN CC path - - 4.5 kOhm Switched capacitance of a reference input CAREFS CC - - 30 pF RMS Noise 7) ENRMS CC - - 1.7 6)8) LSB target Positive reference VAREFx pin leakage IOZ2 CC -6 - 6 µA VAREFx = VAREF2; VAREF>VDDMV; TJ>150°C -3.5 - 3.5 µA VAREFx = VAREF2; VAREF>VDDMV; TJ≤150°C -2 - 2.5 µA VAREFx = VAREF2; VAREF≤VDDMV; TJ>150°C -1 - 1 µA VAREFx = VAREF2; VAREF≤VDDMV; TJ≤150°C -12 - 12 µA VAGNDx = VAGND2; VAGND150°C -6.5 - 6.5 µA VAGNDx = VAGND2; VAGND150°C -1 - 1 µA VAGNDx = VAGND2; VAREF≤VDDMV; TJ≤150°C DNL error 1) Offset Error 1) Switched capacitance of an analog input Negative reference VAGNDx pin leakage IOZ3 CC Resistance of the reference input path RAREF CC - - 3 kOhm CSD resistance 9) RCSD CC - - 28 kOhm Data Sheet 3-354 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationVADC Parameters Table 3-28 VADC_33V (cont’d) Parameter Symbol Values Min. Resistance of the multiplexer diagnostics pull-down device Resistance of the multiplexer diagnostics pull-up device RMDD CC RMDU CC Typ. Unit Note / Test Condition kOhm 0 V ≤ VIN ≤ 1.667 V Max. 25 + 3*VIN - 40 + 12*VIN 0 + 18*VIN - 0 + 18*VIN kOhm 1.667 V ≤ VIN ≤ VDDM 60 12*VIN - 120 30*VIN kOhm 0 V ≤ VIN ≤ 1.667 V 55 - 9*VIN - 95 15*VIN kOhm 1.667 V ≤ VIN ≤ VDDM Resistance of the pull-down test device 10) RPDD CC - - 0.9 kOhm CSD voltage accuracy 11) 12) dVCSD CC - - 10 % Wakeup time tWU CC - 12 µs - 1) If the reference voltage is reduced by the factor k (k < 1), TUE,DNL,INL,Gain, and Offset errors increase also by the factor 1/k. VAREF must be decoupled with an external capacitor. 2) For QCONV = X pC and a conversion time of 1 µs a rms value of X µA results for IAREFx. 3) For the details of the mapping for a VADC group to pin VAREFx please see the User's Manual. 4) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a conversion rate higher than 1 conversion per 500 ms. 5) The broken wire detection delay against VAREF is measured in numbers of consecutive precharge cycles at a conversion rate higher than 1 conversion per 10 ms. This function is influenced by leakage current, in particular at high temperature. 6) Resulting worst case combined error is arithmetic combination of TUE and ENRMS. 7) This parameter is valid for soldered devices and requires careful analog board design. 8) Value is defined for one sigma Gauss distribution. 9) In order to avoid an additional error due to incomplete sampling, the sampling time shall be set greater than 5 * RCSD * CAINS. 10) The pull-down resistor RPDD is connected between the input pad and the analog multiplexer. The input pad itself adds another 200-Ohm series resistance, when measuring through the pin. 11) CSD: Converter Self Diagnostics, for details please consult the User's Manual. 12) Note, that in case CSD voltage is chosen to nom. 1/3 or 2/3 of VAREF voltage, the reference voltage is loaded with a current of max. VAREF / 45 kOhm. RSource V AIN R AIN, On C AINT - C AINS C Ext A/D Converter CAINS MCS05570 Figure 3-2 Equivalent Circuitry for Analog Inputs Data Sheet 3-355 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationDSADC Parameters 3.9 DSADC Parameters The following DSADC parameter are valid for VDDM = 4.5 V to 5.5 V. Table 3-29 DSADC Parameter Symbol Analog input voltage range 1) VDSIN SR Values Unit Note / Test Condition Min. Typ. Max. 0 - 5 V single ended 0 - 10 V differential;VDSxP - VDSxN Reference load current IREF SR - 4.5 5.5 µA Modulator clock frequency 2) fMOD SR 10 - 20 MHz Gain error EDGAIN CC -1 -3.5 DC offset error EDOFF CC 4) Input impedance Signal-Noise Ratio 7) 8) 9) 10) Calibrated once 3.5 % Uncalibrated 5) % calibrated; GAIN = 1; MODCFG.INCFGx=01 mV calibrated mV calibrated once mV gain = 1; uncalibrated - 0.2 -5 - 5 5) -100 6) - % 4) -0.2 -50 Common Mode Rejection Ratio EDCM CC 1 3) 4) 0 50 4) per twin-modulator (1 or 2 channels) 100 4) 200 500 - RDAIN CC 100 130 170 kOhm Exact value (±1%) available in UCB SNR CC 80 - - dB fPB = 30 kHz; VDDM = ±5%; fMOD = 20 MHz; GAIN = 1 78 - - dB fPB = 50 kHz; VDDM = ±5%; fMOD = 20 MHz; GAIN = 1 70 - - dB fPB = 100 kHz; VDDM = ±10%; fMOD = 20 MHz; GAIN = 1 74 - - dB fPB = 100 kHz; VDDM = ±5%; fMOD = 20 MHz; GAIN = 1 76 - - dB fPB = 30 kHz; VDDM = ±10%; fMOD = 20 MHz; GAIN = 1 74 - - dB fPB = 50 kHz; VDDM = ±10%; fMOD = 20 MHz; GAIN = 1 Output data rate fD = fPB * 3 Pass band fPB CC 10 11) - 100 kHz Pass band ripple 8) dfPB CC -1 - 1 % Output sampling rate fD CC 30 - 330 kHz Data Sheet 3-356 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationDSADC Parameters Table 3-29 DSADC (cont’d) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition 10-5 fD DC compensation factor DCF CC -3 - - dB Positive reference VAREF1 pin leakage IOZ5 CC -2 - 2 µA Negative reference VAGND1 pin leakage IOZ6 CC -3 - 2 µA Stop band attenuation 8) SBA CC 40 - - dB 0.5 ... 1 fD 45 - - dB 1 ... 1.5 fD 50 - - dB 1.5 ... 2 fD 55 - - dB 2 ... 2.5 fD 60 - - dB 2.5 ... OSR/2 fD VSSM - - VSSM + V Reference ground voltage Positive reference voltage VAGND SR VAREF SR 0.05 0.05 VDDMnom * - VDDM + 0.9 0.05 V Common mode voltage accuracy dVCM CC -100 - 100 mV from selected voltage Common mode hold voltage deviation 12) dVCMH CC -200 - 200 mV From common mode voltage Analog filter settling time tAFSET CC - 2 4 µs If enabled Modulator recovery time tMREC CC - 3.5 5.5 µs After leaving overdrive state Modulator settling time 13) tMSET CC - 1 - µs After switching on, voltage regulator already running 60 - - dB VCM = 2.2 V, DC coupled; VDDM = ±10% Spurious Free Dynamic Range SFDR CC 7)14) 1) The maximum input range for symmetrical signals (e.g. AC-coupled inputs) depends on the selected internal/external common mode voltage. In this case the Amplitude is limited to VCM * 2. 2) All modulators must run on the same frequency. 3) The calibration sequence must be executed once after an Application Reset 4) The total DC error for the uncalibrated case can be calculated by the geometric addition of EDGAIN and EDOFF 5) Recalibration needed in case of a temperature change > 20ºC 6) The variation of the impedance between different channels is < 1.5%. 7) Derating factors: -2 dB in standard-performance mode. -3 dB for CMV = 10B, i.e. VCM = (VAREF±2%) / 2.0. 8) CIC3, FIR0, FIR1 filters enabled. 9) Single-ended mode reduces the SNR by 6 dB if the unused input is grounded, by 3 dB if the unused input connects to VCM (GAIN = 2). 10) The defined limits are only valid if the following condition is not applicable: TJ > 150°C and VVAREF > VDDM. 11) 10 kHz only reachable with 10 MHz modulator clock frequency. 12) Voltage VCM is proportional to VAREF, voltage VCMH is proportional to VDDM. 13) The modulator needs to settle after being switched on and after leaving the overdrive state. 14) SFDR = 20 * log(INL / 2N); N = amount of bits Data Sheet 3-357 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationDSADC Parameters The following DSADC parameter are valid for VDDM = 2.97 V to 4.5 V. Table 3-30 DSADC_33V Parameter Symbol Analog input voltage range 1) VDSIN SR Values Unit Note / Test Condition Min. Typ. Max. 0 - 3.3 V single ended 0 - 6.6 V differential;VDSxP - VDSxN Reference load current IREF SR - 4.5 5.5 Modulator clock frequency 2) fMOD SR 10 - 20 Gain error EDGAIN CC -1.5 -10 DC offset error Signal-Noise Ratio 7) 8) 9) 10) - MHz 3) 1.5 10 4) 5) % Calibrated once % Uncalibrated % calibrated; GAIN = 1; MODCFG.INCFGx=01 - 0.3 -5 - 5 5) mV calibrated -50 - 50 mV calibrated once -100 4) 04) 100 4) mV gain = 1; uncalibrated 200 500 - RDAIN CC 100 130 170 kOhm Exact value (±1%) available in UCB SNR CC 45 63 - dB fPB = 100kHz; VDDM = ±10%; fMOD = 20 MHz; GAIN = 1 60 69 - dB fPB = 100kHz; VDDM = ±5%; fMOD = 20 MHz; GAIN = 1 60 68 - dB fPB = 30kHz; VDDM = ±10%; fMOD = 20 MHz; Common Mode Rejection Ratio EDCM CC Input impedance - per twin-modulator (1 or 2 channels) -0.3 EDOFF CC 6) 4) µA GAIN = 1 69 74 - dB fPB = 30kHz; VDDM = ±5%; fMOD = 20 MHz; GAIN = 1 55 66 - dB fPB = 50kHz; VDDM = ±10%; fMOD = 20 MHz; GAIN = 1 65 72 - dB fPB = 50kHz; VDDM = ±5%; fMOD = 20 MHz; GAIN = 1 Pass band fPB CC 10 11) - 100 kHz Output data rate fD = fPB * 3 Pass band ripple 8) dfPB CC -1 - 1 % Output sampling rate fD CC 30 - 330 kHz DC compensation factor DCF CC -3 - - dB Data Sheet 3-358 10-5 fD V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationDSADC Parameters Table 3-30 DSADC_33V (cont’d) Parameter Symbol Values Unit Min. Typ. Max. Note / Test Condition Positive reference VAREF1 pin leakage IOZ5 CC -2 - 2 µA Negative reference VAGND1 pin leakage IOZ6 CC -3 - 2 µA Stop band attenuation 8) SBA CC 40 - - dB 0.5 ... 1 fD 45 - - dB 1 ... 1.5 fD 50 - - dB 1.5 ... 2 fD 55 - - dB 2 ... 2.5 fD 60 - - dB 2.5 ... OSR/2 fD VSSM - - VSSM + V Reference ground voltage Positive reference voltage VAGND SR VAREF SR 0.05 0.05 VDDMnom * - VDDM + 0.9 0.05 V Common mode voltage accuracy dVCM CC -100 - 100 mV from selected voltage Common mode hold voltage deviation 12) dVCMH CC -200 - 200 mV From common mode voltage Analog filter settling time tAFSET CC - 2 4 µs If enabled Modulator recovery time tMREC CC - 3.5 - µs After leaving overdrive state Modulator settling time 13) tMSET CC - 1 - µs After switching on, voltage regulator already running 52 - - dB VCM = 2.2 V, DC coupled; VDDM = ±10% 60 - - dB VCM = 2.2 V, DC coupled; VDDM = ±5% Spurious Free Dynamic Range SFDR CC 7)14) 1) The maximum input range for symmetrical signals (e.g. AC-coupled inputs) depends on the selected internal/external common mode voltage. In this case the Amplitude is limited to VCM * 2. 2) All modulators must run on the same frequency. 3) The calibration sequence must be executed once after an Application Reset 4) The total DC error for the uncalibrated case can be calculated by the geometric addition of EDGAIN and EDOFF 5) Recalibration needed in case of a temperature change > 20ºC. 6) The variation of the impedance between different channels is < 1.5%. 7) Derating factors: -2 dB in standard-performance mode. -3 dB for CMV = 10B, i.e. VCM = (VAREF±2%) / 2.0. 8) CIC3, FIR0, FIR1 filters enabled. 9) Single-ended mode reduces the SNR by 6 dB if the unused input is grounded, by 3 dB if the unused input connects to VCM (GAIN = 2). 10) The defined limits are only valid if the following condition is not applicable: TJ > 150°C and VVAREF > VDDM. 11) 10 kHz bandwidth only with 10Mhz modulator clock frequency reachable 12) Voltage VCM is proportional to VAREF, voltage VCMH is proportional to VDDM. 13) The modulator needs to settle after being switched on and after leaving the overdrive state. Data Sheet 3-359 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationDSADC Parameters 14) SFDR = 20 * log(INL / 2N); N = amount of bits 37 kΩ 37 kΩ V CM Gain Input V OFFSET 130 kΩ = 130 kΩ Modu lator Gain MC_DSADC_MODULATORBLOCK Figure 3-3 DSADC Analog Inputs Data Sheet 3-360 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationMHz Oscillator 3.10 MHz Oscillator OSC_XTAL is used as accurate and exact clock source. OSC_XTAL supports 8 MHz to 40 MHz crystals external outside of the device. Support of ceramic resonators is also provided. Table 3-31 OSC_XTAL Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Input current at XTAL1 IIX1 CC -25 - 25 µA VIN>0V; VIN 25MHz V If shaper is not bypassed; fOSC ≤ 25MHz 0.5 Input low voltage at XTAL1 VILBX SR -0.5 - Input voltage at XTAL1 VIX SR -0.5 - 0.5 Input amplitude (peak to peak) VPPX SR at XTAL1 0.3 * - 1.0 VDDP3 0.4 * VDDP3 + - VDDP3 + 1.0 VDDP3 Internal load capacitor CL0 CC 2 2.35 2.7 pF Internal load capacitor CL1 CC 2 2.35 2.7 pF Internal load capacitor CL2 CC 3 3.5 4 pF Internal load capacitor CL3 CC 5.1 5.9 6.6 pF 1) tOSCS is defined from the moment when VDDP3 = 3.13V until the oscillations reach an amplitude at XTAL1 of 0.3 * VDDP3. The external oscillator circuitry must be optimized by the customer and checked for negative resistance as recommended and specified by crystal suppliers. 2) This value depends on the frequency of the used external crystal. For faster crystal frequencies this value decrease. Note: It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits specified by the crystal or ceramic resonator supplier. Data Sheet 3-361 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationBack-up Clock 3.11 Back-up Clock The back-up clock provides an alternative clock source. Table 3-32 Back-up Clock Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. 75 100 125 MHz VEXT≥2.97V Slow speed Back-up clock fBACKSS CC 75 100 125 kHz VEXT≥2.97V Back-up clock after trimming fBACKT CC 100 102.5 MHz VEXT≥2.97V Back-up clock before trimming fBACKUT CC Data Sheet 97.5 3-362 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationTemperature Sensor 3.12 Temperature Sensor Table 3-33 DTS Parameter Symbol Values Unit Min. Typ. Max. - - 100 µs Calibration reference accuracy TCALACC CC -1 - 1 °C Non-linearity accuracy over temperature range TNL CC -2 - 2 °C Temperature sensor range TSR SR -40 - 170 °C Start-up time after resets inactive tTSST SR - - 20 µs Measurement time tM CC Note / Test Condition calibration points @ TJ=-40°C and TJ=127°C The following formula calculates the temperature measured by the DTS in [oC] from the RESULT bit field of the DTSSTAT register. (3.1) DTSSTATRESULT – ( 607 ) Tj = ---------------------------------------------------------------------------2, 13 Data Sheet 3-363 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationPower Supply Current 3.13 Power Supply Current The total power supply current defined below consists of leakage and switching component. Application relevant values are typically lower than those given in the following table and depend on the customer's system operating conditions (e.g. thermal connection or used application configurations). The operating conditions for the parameters in the following table are: The real (realisic) power pattern defines the following conditions: • • TJ = 150 °C fCPU0 = 200 MHz fSRI = fMAX = fCPU1 = fCPU2 300 MHz fSPB = fSTM = fGTM = fBAUD1 = fBAUD2 = fASCLIN = 50 MHz VDD = 1.326 V VDDP3 = 3.366 V VEXT / FLEX = VDDM = 5.1 V • all cores are active including one lockstep core • the following peripherals are inactive: EBU, HSM, HSCT, Ethernet, PSI5, I2C, FCE, MTU, and 50% of the DSADC channels • • • • • The max power pattern defines the following conditions: • • TJ = 150 °C fCPU0 = 200 MHz fSRI = fMAX = fCPU1 = fCPU2 300 MHz fSPB = fSTM = fGTM = fBAUD1 = fBAUD2 = fASCLIN = 100 MHz VDD = 1.43 V VDDP3 = 3.63 V VEXT / FLEX = VDDM = 5.5 V • all cores and lockstep cores are active • all peripherals are active • • • • • Data Sheet 3-364 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationPower Supply Current Table 3-34 Power Supply Parameter ∑ Sum of IDD 1.3 V core and peripheral supply currents Data Sheet Symbol IDD CC Values Unit Note / Test Condition Min. Typ. Max. - - 750 mA max power pattern with fSRI/CPUx = 270 MHz with VDD = 1.3V + 10%; valid for Feature Package T, TP, and TC products - - 800 mA max power pattern with fSRI/CPUx = 300 MHz with VDD = 1.33V + 7.5%. valid for Feature Package T, TP, and TC products - - 950 mA max power pattern. valid for Feature Package TA and TB products - - 930 mA max power pattern. valid for Feature Package TX and TY products - - 567 mA real power pattern. valid for Feature Package T, TP, and TC products - - 637 mA real power pattern. valid for Feature Package TA, TB, TX and TY products 3-365 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationPower Supply Current Table 3-34 Power Supply (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. - - 140 mA valid for Feature Package T, TP, and TC products; TJ=125°C - - 220 mA valid for Feature Package T, TP, and TC products; TJ=150°C - - 176 mA valid for Feature Package TA, TB, TX, and TY products; TJ=125°C - - 310 mA valid for Feature Package T, TP, and TC products; TJ=165°C - - 290 mA valid for Feature Package TA, TB, TX, and TY products; TJ=150°C - - 405 mA valid for Feature Package TA, TB, TX, and TY products; TJ=165°C IDD core current of CPU1 main IDDC10 CC core with CPU1 lockstep core inactive - - 62 mA real power pattern IDD core current of CPU1 main IDDC11 CC core with lockstep core active - - IDDC10 + mA real power pattern IDD core current of CPU2 main IDDC20 CC core - - 60 mA real power pattern IDD core current added by HSM IDDHSM CC - - 20 mA HSM running at 100MHz. IDD core current added by AMU IDDAMU CC - - 48 mA real power pattern IDD core current added by FFT IDDFFT CC - - 40 mA FFT running at 200MHz ∑ Sum of 3.3 V supply currents IDDx3RAIL CC without pad activity - 104 1) mA real power pattern IDDFL3 Flash memory current - 84 2) mA flash read current - 3) mA flash read current while programming Dflash IDD core current during active power-on reset (PORST held low) IDDPORST CC IDDFL3 CC 48 - Data Sheet 3-366 84 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationPower Supply Current Table 3-34 Power Supply (cont’d) Parameter IDDP3 supply current without Symbol IDDP3 CC Values Unit Note / Test Condition Min. Typ. Max. - - 29 2) mA real power pattern; incl. OSC & flash read current - - 46 3) mA incl. OSC and flash programming current - - 46 4) mA incl. OSC current and flash 3.3V programming current when using external 5V supply pad activity IDDP3 supply current for LVDSH IDDP3LVDSH - - 16 mA pads in LVDS mode CC Σ Sum of external and ADC supply currents (incl. IEXTFLEX+IDDM+IEXTLVDSM) IEXTRAIL CC - - 98 mA real power pattern Sum of IEXT and IFLEX supply current without pad activity IEXT/FLEX CC - - 16 mA real power pattern; PORST output inactive. - - 20 5) mA real power pattern - - 62 mA real power pattern; sum of currents of DSADC and VADC modules - - 52 mA current for DSADC module only; 50% DSADC channels active. - - 100 6) mA max power pattern; All DSADC channels active 100% time. - - 10 mA real pattern; current for VADC only - - 20 7) mA max power pattern; All VADC converters are active 100% time - - 770 mA real power pattern; valid for Feature Package T, TP, and TC products - - 840 mA real power pattern; valid for Feature Package TA, TB, TX, and TY products IEXT supply current for LVDSM IEXTLVDSM pads in LVDS mode CC IDDM supply current IDDM CC Σ Sum of all currents (incl. IEXTRAIL+IDDx3RAIL+IDD) Data Sheet IDDTOT CC 3-367 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationPower Supply Current Table 3-34 Power Supply (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. - - 460 mA real power pattern; VEXT = 3.3V - - 370 mA real power pattern; VEXT = 5V Σ Sum of all currents with DCDC EVR13 regulator active 8) IDDTOTDC3 Σ Sum of all currents with DCDC EVR13 regulator active 8) IDDTOTDC5 ∑ Sum of all currents (STANDBY mode) IEVRSB CC - - 150 9) µA Standby RAM is active. Power to remaining domains switched off. TJ = 25°C; VEVRSB = 5V ∑ Sum of all currents (SLEEP mode) ISLEEP CC - - 24 mA All CPUs in idle, All peripherals in sleep, fSRI/SPB = 1 MHz via LPDIV divider; TJ = 25°C; valid for Feature Package T, TP, and TC products - - 26 mA All CPUs in idle, All peripherals in sleep, fSRI/SPB = 1 MHz via LPDIV divider; TJ = 25°C; valid for Feature Package TA, TB, TX, and TY products - - 2382 mW max power pattern ; valid for Feature Package TA and TB products - - 2140 mW max power pattern. valid for Feature Package T, TP, and TC products - - 2350 mW max power pattern. valid for Feature Package TX and TY products - - 1600 mW real power pattern. valid for Feature Package T, TP, and TC products - - 1700 mW real power pattern. valid for Feature Package TA, TB, TX, and TY products Maximum power dissipation CC CC PD CC 1) In case EVR33 is not used, Injection current into 3.3V VDDP3 supply rail with active sink on 5V VEXT rail should be limited to 500 mA if during power sequencing 3.3V is supplied before 5V by external regulator. Data Sheet 3-368 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationPower Supply Current 2) Realistic Pflash read pattern with 70% Pflash bandwidth utlilization and a code mix of 50% 0s and 50% 1s. A common decoupling capacitor of atleast 100nF for (VDDFL3+VDDP3) is used. Dflash read current is also included. Flash read current is predominantly drawn from VDDFL3 pin and a minor part drawn from the neighbouring VDDP3 pin. 3) Continuous Dflash programming in burst mode with 3.3 V supply and realistic Pflash read access in parallel. Erase currents of the corresponding flash modules are less than the respective programming currents at VDDP3 pin. Programming and erasing flash may generate transient current spikes of up to x mA for maximum x us which is handled by the decoupling and buffer capacitors. This parameter is relevant for external power supply dimensioning and not for thermal considerations. 4) In addition to the current specified, upto 4 mA is additionally drawn at VEXT supply in burst programming mode with 5V external supply. Erase currents of the corresponding flash modules are less than the respective programming currents at VDDP3 supply. This parameter is relevant for external power supply dimensioning and not for thermal considerations. 5) The current consumption is for 2 pairs of LVDSM differential pads (8 pins). A single pair of LVDSM differential pads (4 pins) consumes 7 mA. 6) The current consumption is for 6 DS channels with standard performance (MCFG=11b). A single DS channel instance consumes 6-8 mA. 7) A single converter instance of VADC unit consumes 2 mA. 8) The total current drawn from external regulator is estimated with 72% EVR13 SMPS regulator Efficiency. IDDTOTDCx is calculated from IDDTOT using the scaled core current [(IDD x VDD)/(VinxEfficiency)] and constitutes all other rail currents and IDDM. 9) Σ Sum of all currents during RUN mode at VEVRSB supply pin is less than (8 mA + ISCRSB) . It is recommended to have atleast 100 nF decoupling capacitor at this pin. 3.13.1 Calculating the 1.3 V Current Consumption The current consumption of the 1.3 V rail compose out of two parts: • Static current consumption • Dynamic current consumption The static current consumption is related to the device temperature TJ and the dynamic current consumption depends of the configured clocking frequencies and the software application executed. These two parts needs to be added in order to get the rail current consumption. Valid for Feature Package T, TP, and TC products: (3.2) mA I 0 = 0, 894 --------- × e 0, 0289 × T J [ C ] C (3.3) mA I 0 = 4, 319 --------- × e 0, 0259 × T J [ C ] C Valid for Feature Package TA, TB, TX, and TY products: (3.4) mA I 0 = 2, 731 --------- × e 0, 0244 × T J [ C ] C (3.5) mA I 0 = 5, 832 --------- × e 0, 0257 × T J [ C ] C Data Sheet 3-369 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationPower Supply Current Function 2 / 4 defines the typical static current consumption and Function 3 / 5 defines the maximum static current consumption. Both functions are valid for VDD = 1.326 V. Data Sheet 3-370 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationPower-up and Power-down 3.14 Power-up and Power-down 3.14.1 External Supply Mode 5 V & 1.3 V supplies are externally supplied. 3.3V is generated internally by EVR33. • External supplies VEXT and VDD may ramp-up or ramp-down independent of each other with regards to start, rise and fall time(s). Voltage Ramp-up from a residual threshold (Eg : up to 1 V) should also lead to a normal startup of the device. • The rate at which current is drawn from the external regulator (dIEXT /dt or dIDD /dt) is limited in the Start-up phase to a maximum of 50 mA/100 us. • PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted. • PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It is recommended to keep the PORST (input) asserted until all the external supplies are above their primary reset thresholds. • PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus propagating the reset to external devices. The PORST (output) is asserted by the µC when atleast one among the three supply domains (1.3 V, 3.3 V or 5 V) violate their primary under-voltage reset thresholds.The PORST (output) is deasserted by the µC when all supplies are above their primary reset thresholds and the basic supply and clock infrastructure is available. • The power sequence as shown in Figure 3-4 is enumerated below – T1 refers to the point in time when basic supply and clock infrastructure is available as the external supplies ramp up. The supply mode is evaluated based on the HWCFG [0:2] pins and consequently a soft start of EVR33 regulator is initiated. – T2 refers to the point in time when all supplies are above their primary reset thresholds. EVR33 regulator has ramped up. PORST (output) is deasserted and HWCFG [0:7] pins are latched on PORST rising edge. Firmware execution is initiated. – T3 refers to the point in time when Firmware execution is completed. User code execution starts with a default frequency of 100 MHz. – T4 refers to the point in time during the Ramp-down phase when atleast one of the externally provided or generated supplies (1.3 V, 3.3 V or 5 V) drop below their respective primary under-voltage reset thresholds. Please note that there is no special requirements for PORST slew rates. Data Sheet 3-371 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationPower-up and Power-down VEXT (externally supplied ) 0 1 2 3 4 5.5 V 5.0 V 4.5 V 2.97 V Primary Reset Threshold 0V VDD (externally supplied ) 1.33 V 1.30 V 1.17 V Primary Reset Threshold 0V PORST (output ) PORST (input) VDDP3 (internally generated by EVR33) 3.63 V 3.30 V 2.97 V Primary Reset Threshold 0V T0 T2 T1 Basic Supply & Clock Infrastructure EVR33 Ramp-up Phase T3 Firmware Execution User Code Execution fCPU =100MHz default on firmware exit T4 Power Ramp-down phase Startup_Diag_1 v 0.1 Figure 3-4 External Supply Mode - 5 V and 1.3 V externally supplied Data Sheet 3-372 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationPower-up and Power-down 3.14.2 Single Supply Mode 5 V single supply mode. 1.3 V & 3.3 V are generated internally by EVR13 & EVR33. • The rate at which current is drawn from the external regulator (dIEXT /dt) is limited in the Start-up phase to a maximum of 50 mA/100 us. • PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted. • PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It is recommended to keep the PORST (input) asserted until the external supply is above the respective primary reset threshold. • PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus propagating the reset to external devices. The PORST (output) is asserted by the µC when atleast one among the three supply domains (1.3 V, 3.3 V or 5 V) violate their primary under-voltage reset thresholds.The PORST (output) is deasserted by the µC when all supplies are above their primary reset thresholds and the basic supply and clock infrastructure is available. • The power sequence as shown in Figure 3-5 is enumerated below – T1 refers to the point in time when basic supply and clock infrastructure is available as the external supply ramps up. The supply mode is evaluated based on the HWCFG [0:2] pins and consequently a soft start of EVR13 and EVR33 regulators are initiated. – T2 refers to the point in time when all supplies are above their primary reset thresholds. EVR13 and EVR33 regulators have ramped up. PORST (output) is deasserted and HWCFG [0:7] pins are latched on PORST rising edge. Firmware execution is initiated. – T3 refers to the point in time when Firmware execution is completed. User code execution starts with a default frequency of 100 MHz. – T4 refers to the point in time during the Ramp-down phase when atleast one of the externally provided or generated supplies (1.3 V, 3.3 V or 5 V) drop below their respective primary under-voltage reset thresholds. Please note that there is no special requirements for PORST slew rates. Data Sheet 3-373 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationPower-up and Power-down VEXT (externally supplied ) 0 1 2 3 4 5.5 V 5.0 V 4.5 V 2.97 V Primary Reset Threshold 0V PORST (output ) PORST (input) VDD 1.33 V (internally generated by EVR13) 1.30 V 1.17 V Primary Reset Threshold 0V VDDP3 (internally generated by EVR33) 3.63 V 3.30 V 2.97 V Primary Reset Threshold 0V T0 T1 Basic Supply & Clock Infrastructure T2 EVR13 & EVR 33 Ramp-up Firmware Execution Phase T3 User Code Execution fCPU =100MHz default on firmware exit T4 Power Ramp-down phase Startup_Diag_2 v 0.1 Figure 3-5 Single Supply Mode - 5 V single supply Data Sheet 3-374 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationPower-up and Power-down 3.14.3 External Supply Mode All supplies, namely 5 V, 3.3 V & 1.3 V, are externally supplied. • External supplies VEXT ,, VDDP3 & VDD may ramp-up or ramp-down independent of each other with regards to start, rise and fall time(s). • The rate at which current is drawn from the external regulator (dIEXT /dt, dIDD /dt or dIDDP3 /dt) is limited in the Start-up phase to a maximum of 50 mA/100 us. • PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted. • PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It is recommended to keep the PORST (input) asserted until all the external supplies are above their primary reset thresholds. • PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus propagating the reset to external devices. The PORST (output) is asserted by the µC when atleast one among the three supply domains (1.3 V, 3.3 V or 5 V) violate their primary under-voltage reset thresholds.The PORST (output) is deasserted by the µC when all supplies are above their primary reset thresholds and the basic supply and clock infrastructure is available. • The power sequence as shown in Figure 3-6 is enumerated below – T1 refers to the point in time when all supplies are above their primary reset thresholds and basic clock infrastructure is available. The supply mode is evaluated based on the HWCFG [0:2] pins. PORST (output) is deasserted and HWCFG [0:7] pins are latched on PORST rising edge. Firmware execution is initiated. – T2 refers to the point in time when Firmware execution is completed. User code execution starts with a default frequency of 100 MHz. – T3 refers to the point in time during the Ramp-down phase when atleast one of the externally provided supplies (1.3 V, 3.3 V or 5 V) drop below their respective primary under-voltage reset thresholds. Please note that there is no special requirements for PORST slew rates. Data Sheet 3-375 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationPower-up and Power-down VEXT (externally supplied ) 0 1 2 3 5.5 V 5.0 V 4.5 V 2.97 V Primary Reset Threshold 0V VDD (externally supplied ) 1.33 V 1.30 V 1.17 V Primary Reset Threshold 0V VDDP3 (externally supplied) 3.63 V 3.30 V 2.97 V Primary Reset Threshold 0V PORST (output ) PORST (input) T0 T1 Basic Supply & Clock Infrastructure T3 T2 User Code Execution fCPU =100 MHz default on firmware exit Firmware Execution Power Ramp-down phase Startup_Diag_3 v 0.1 Figure 3-6 External Supply Mode - 5 V, 3.3 V & 1.3 V externally supplied Data Sheet 3-376 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationPower-up and Power-down 3.14.4 Single Supply Mode 3.3 V single supply mode. 1.3 V is generated internally by EVR13. • The rate at which current is drawn from the external regulator (dIEXT /dt) is limited in the Start-up phase to a maximum of 50 mA/100 us. • PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted. • PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It is recommended to keep the PORST (input) asserted until the external supply is above the respective primary reset threshold. • PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus propagating the reset to external devices. The PORST (output) is asserted by the µC when atleast one among the three supply domains (1.3 V or 3.3 V) violate their primary under-voltage reset thresholds.The PORST (output) is deasserted by the µC when all supplies are above their primary reset thresholds and the basic supply and clock infrastructure is available. • The power sequence as shown in Figure 3-7 is enumerated below – T1 refers to the point in time when basic supply and clock infrastructure is available as the external supply ramps up. The supply mode is evaluated based on the HWCFG [0:2] pins and consequently a soft start of EVR13 regulator is initiated. – T2 refers to the point in time when all supplies are above their primary reset thresholds. EVR13 regulator has ramped up. PORST (output) is deasserted and HWCFG [0:7] pins are latched on PORST rising edge. Firmware execution is initiated. – T3 refers to the point in time when Firmware execution is completed. User code execution starts with a default frequency of 100 MHz. – T4 refers to the point in time during the Ramp-down phase when atleast one of the externally provided or generated supplies (1.3 V or 3.3 V) drop below their respective primary under-voltage reset thresholds. Please note that there is no special requirements for PORST slew rates. Data Sheet 3-377 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationPower-up and Power-down VEXT (externally supplied ) 0 & VDDP3 (externally supplied ) 1 2 3 4 T3 User Code Execution fCPU =100MHz default on firmware exit T4 3.63 V 3.30 V 2.97 V Primary Reset Threshold 0V PORST (output ) PORST (input) VDD (internally generated 1.33 V 1.30 V 1.17 V by EVR 13) Primary Reset Threshold 0V T2 T1 T0 Basic Supply & Clock Infrastructure EVR13 Ramp-up Phase Firmware Execution Power Ramp-down phase Startup_Diag_4 v 0.1 Figure 3-7 Single Supply Mode - 3.3 V single supply Data Sheet 3-378 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationReset Timing 3.15 Reset Timing Table 3-35 Reset Timings Parameter Symbol Application Reset Boot Time 1) System Reset Boot Time Power on Reset Boot Time 3) Values Note / Test Condition operating with max. frequencies. Min. Typ. Max. tB CC - - 350 2) µs tBS CC - - 1 ms tBP CC - - 2.5 - - tEVRstartup 2) ms dV/dT=1V/ms. including EVR rampup and Firmware execution time 1.11 2) ms Firmware execution time; without EVR operation (external supply only) - - µs - - 1 ms 1 - - ms - 1200 ns Minimum PORST hold time tEVRPOR CC 10 incase of power fail event issued by EVR primary monitor EVR start-up or ramp-up time Unit CC Minimum PORST active hold time after power supplies are stable at operating levels 4) tPOA CC tPORSTDF CC 600 Configurable PORST digital filter delay in addition to analog pad filter delay HWCFG pins hold time from ESR0 rising edge tHDH CC 16 / fSPB - - ns HWCFG pins setup time to ESR0 rising edge tHDS CC 0 - - ns Ports inactive after ESR0 reset tPI CC active - - 8/fSPB ns Ports inactive after PORST reset active 5) tPIP CC - - 150 ns Hold time from PORST rising edge tPOH SR 150 - - ns Setup time to PORST rising edge tPOS SR 0 - - ns dV/dT=1V/ms. EVR13 and EVR33 active 1) The duration of the boot time is defined between the rising edge of the internal application reset and the clock cycle when the first user instruction has entered the CPU pipeline and its processing starts. 2) The timing values assumes programmed BMI with ESR0CNT inactive. 3) The duration of the boot time is defined by all external supply voltages are inside there operation condictions and the clock cycle when the first user instruction has entered the CPU pipeline and its processing starts. Data Sheet 3-379 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationReset Timing 4) The regulator that supplies VEXT should ensure that VEXT is in the operational region before PORST is externally released by the regulator. Incase of 5V nominal supply, it should be ensured that VEXT > 4V before PORST is released. Incase of 3.3V nominal supply , it should be ensured that VEXT > 3V before PORST is released. The additional minimum PORST hold time is required as an additional mechanism to avoid consecutive PORST toggling owing to slow supply slopes or residual supply ramp-ups. It is also required to activate external PORST atleast 100us before power-fail is recognised to avoid consecutive PORST toggling on a power fail event. 5) This parameter includes the delay of the analog spike filter in the PORST pad. VDDP V D DPPA VDD PPA V DDPR VDD tPOA tPOA PORST Warm Cold ESR0 t PI tP I tP IP Tristate Z / pullup H Pads Programmed Z/ H Programmed Z /H Programmed Padstate undefined TRST Padstate undefined t P OS t P OS t P OH tP OH TESTMODE t HDH HWCFG power -on config t HDA t HDH config t HDA t HDH config reset_beh_aurix Figure 3-8 Power, Pad and Reset Timing Data Sheet 3-380 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationEVR 3.16 EVR Table 3-36 3.3V Parameter Input voltage range Symbol 1) Output voltage operational range including load/line regulation and aging incase of LDO regulator VIN SR VOUT CC VOUTT CC Output VDDx3 static voltage accuracy after trimming and aging without dynamic load/line Regulation incase of LDO regulator. Output buffer capacitance on VOUT 2) COUT CC Values Unit Note / Test Condition Min. Typ. Max. - - 5.50 V pass device=off chip 4 - 5.50 V pass device=on chip 2.97 3.3 3.63 V pass device=off chip 2.97 3.3 3.63 V pass device=on chip 3.225 3.3 3.375 V pass device=off chip 3.225 3.3 3.375 V pass device=on chip - 2.2 - µF pass device=off chip - 2.2 - µF pass device=on chip Primary Undervoltage Reset threshold for VDDx3 3) VRST33 CC - - 3.0 V by reset release before EVR trimming on supply ramp-up. Startup time tSTR CC - - 1000 µs pass device=off chip - - 1000 µs pass device=on chip dVin/dT - 1 50 V/ms pass device=off chip SR - 1 50 V/ms pass device=on chip dVout/dIout - - 240 mV dI=-100mA; Tsettle=20µs; pass External VIN supply ramp 4) Load step response CC device=off chip - - 240 mV dI=-70mA/20ns; Tsettle=20us; pass device=on chip -240 - - mV dI=100mA; Tsettle=20µs; pass device=off chip -240 - - mV dI=50mA/20ns; Tsettle=20us; pass device=on chip Line step response dVout/dVin -20 - 20 mV CC dV/dT=1V/ms; pass device=off chip -20 - 20 mV dV/dT=1V/ms; pass device=on chip 1) A maximum pass device dropout voltage of 700mV is included in the minimum input voltage to ensure optimal pass device operation. Data Sheet 3-381 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationEVR 2) It is recommended to select a capacitor with ESR less than 50 mOhm (0.5MHz - 10 MHz). It is also recommended that the resistance of the supply trace from the pin to the EVR output capacitor is less than 100 mOhm. 3) The reset release on supply ramp-up is delayed by a time duration 20-40 us after reaching undervoltage reset threshold. This serves as a time hysteresis to avoid multiple consecutive cold PORST events during slow supply ramp-ups owing to voltage drop/current jumps when reset is released. The reset limit of 2,97V at pin is for the case with 3.3V generated internally from EVR33. In case the 3.3V supply is provided externally, the bondwire drop will cause a reset at a higher voltage of 3.0V at the VDDP3 pin. 4) EVR robust against residual voltage ramp-up starting between 0-1 V. Table 3-37 1.3V Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. VIN SR 2.97 - 5.5 V pass device=off chip VOUT CC 1.17 1.3 1.43 V pass device=off chip VOUTT CC Output VDD static voltage accuracy after trimming without dynamic load/line regulation with aging incase of LDO regulator. 1.275 1.3 1.325 V pass device=off chip Output buffer capacitance on COUT CC 3 4.7 6.3 µF pass device=off chip Primary undervoltage reset threshold for VDD 3) VRST13 CC - - 1.17 V by reset release before EVR trimming on supply ramp-up. pass device=off chip Startup time tSTR CC - - 1000 µs pass device=off chip dVin/dT - 1 50 V/ms pass device=off chip dVout/dIout - - 100 mV dI=-150mA; Tsettle=20µs; pass Input voltage range 1) Output voltage operational range including load/line regulation and aging incase of LDO regulator VOUT 2) External VIN supply ramp 4) SR Load step response CC device=off chip -100 - - mV dI=100mA; Tsettle=20µs; pass device=off chip Line step response dVout/dVin -10 - CC 10 mV dV/dT=1V/ms; pass device=off chip 1) A maximum pass device dropout voltage of 700mV is included in the minimum input voltage to ensure optimal pass device operation. 2) It is recommended to select a capacitor with ESR less than 50 mOhm (0.5MHz - 10 MHz). It is also recommended that the resistance of the supply trace from the pin to the EVR output capacitor is less than 100 mOhm. 3) The reset release on supply ramp-up is delayed by a time duration 30-60 µs after reaching undervoltage reset threshold. This serves as a time hysteresis to avoid multiple consecutive cold PORST events during slow supply ramp-ups owing to voltage drop/current jumps when reset is released.The reset limit of 1,17V at pin is for the case with 1.3V generated internally from EVR13. In case the 1.3V supply is provided externally, the bondwire drop will cause a reset at a higher voltage of 1.18V at the VDD pin. 4) EVR robust against residual voltage ramp-up starting between 0-1 V. Data Sheet 3-382 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationEVR Table 3-38 Supply Monitoring Parameter Symbol VEXT primary undervoltage VEXTPRIUV monitor accuracy after trimming 1) SR VDDP3 primary undervoltage monitor accuracy after trimming 1) VDDP3PRIUV Values Unit Note / Test Condition Min. Typ. Max. 2.86 2.92 2.97 V VEXT = Undervoltage Reset Threshold 2.86 2.90 2.97 V VDDP3 = Undervoltage Reset Threshold 1.13 1.15 1.17 V VDD = Undervoltage SR VDD primary undervoltage VDDPRIUV monitor accuracy after trimming 1) SR Reset Threshold VEXT secondary supply monitor VEXTMON CC 4.9 5.0 5.1 V SWDxxVAL VEXT monitoring threshold=5V=DAh 3.23 3.30 3.37 V EVR33xxVAL VDDP3 monitoring threshold=3.3V=90h VDD secondary supply monitor VDDMON CC 1.27 1.30 1.33 V EVR13xxVAL VDD monitoring threshold=1.3V=DFh - 1.8 µs accuracy VDDP3 secondary supply VDDP3MON monitor accuracy CC accuracy EVR primary and secondary monitor measurement latency for a new supply value tEVRMON CC - 1) The monitor tolerances constitute the inherent variation of the bandgap and ADC over process, voltage and temperature operational ranges. The xxxPRIUV parameters are device individually tested in production with ±1% tolerance about the min and max xxxPRIUV limits. In TQFP100 and QFP80 pin packages, VDDPRIUV is not tested as HWCFG2 pin is absent. Table 3-39 EVR13 SMPS External components Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. 15.4 22 29.7 µF IDDDC=1A 6.5 10 13.5 µF IDDDC=400mA External output capacitor ESR CDC_ESR SR - - 50 mOhm f≥0.5MHz; f≤10MHz - - 100 Ohm f=10Hz 6.5 10 13.5 µF IDDDC=1A 4.42 6.8 9.18 µF IDDDC=400mA CIN_ESR SR - - 50 mOhm f≥0.5MHz; f≤10MHz - - 100 Ohm f=100Hz 2.31 3.3 4.29 µH fDCDC=1.5MHz 3.29 4.7 6.11 µH fDCDC=1MHz External output capacitor value COUTDC SR 1) External input capacitor value External input capacitor ESR External inductor value 2) 1) CIN SR LDC SR External inductor ESR LDC_ESR SR - - 0.2 Ohm P + N-channel MOSFET logic level VLL SR - 2.5 V Data Sheet - 3-383 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationEVR Table 3-39 EVR13 SMPS External components (cont’d) Parameter Symbol Values Min. Unit Typ. Max. Note / Test Condition P + N-channel MOSFET drain source breakdown voltage |VBR_DS| SR - - 7 V P + N-channel MOSFET drain source ON-state resistance RON SR - - 150 mOhm IDDDC=1A;VGS=2.5V ; TA=25°C - - 200 mOhm IDDDC=400mA;VGS=2.5 V ; TA=25°C - 4 - nC IDDDC=1A; MOSVGS=5V - 8 - nC IDDDC=400mA; MOSVGS=5V configurable P + N-channel MOSFET Gate Charge Qac SR External MOSFET commutation time tc SR 10 30 40 ns N-channel MOSFET reverse diode forward voltage VRDN SR - 0.8 - V 1) Capacitor min-max range represent typical ±35% tolerance including DC bias effect. The trace resistance from the capacitor to the supply or ground rail should be limited to 25 mOhm. 2) External inductor min-max range represent typical ±30% tolerance at a DC bias current of 100mA. Table 3-40 EVR13 SMPS Parameter Symbol Values Unit Min. Typ. Max. Note / Test Condition Input VDDP3 voltage range VIN CC 2.97 - 3.63 V Input VEXT Voltage range VIN SR 2.97 - 5.5 V SMPS regulator output voltage VDDDC CC range including load/line regulation and aging 1) 1.17 - 1.43 V VDD≥2.97V; VDD≤5.5V; IDDDC≥1mA; IDDDC≤1A SMPS regulator static voltage VDDDCT CC output accuracy after trimming without dynamic load/line Regulation with aging. 2) 1.275 1.3 1.325 V VDD≥2.97V; VDD≤5.5V; IDDDC≥1mA; IDDDC≤1A 0.4 - 2.0 MHz Programmable switching frequency fDCDC CC Switching frequency modulation spread ∆fDCSPR CC - - 2% MHz Maximum ripple at IMAX (peak- ∆VDDDC CC to-peak) 3) - 15 mV VDD≥2.97V; VDD≤5.5V; IDDDC≥300mA; IDDDC≤1A No load current consumption of IDCNL CC SMPS regulator 5 10 mA fDCDC=1MHz Data Sheet - 3-384 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationEVR Table 3-40 EVR13 SMPS (cont’d) Parameter Symbol Values Min. Unit Note / Test Condition Typ. Max. - 25 mV dI < 200mA ; fDCDC=1MHz; tr=0.1µs; tf=0.1µs; VDDDC=1.3V -65 - 65 mV dI < 400mA ; fDCDC=1MHz; tr=0.1µs; tf=0.1µs; VDDDC=1.3V -130 - 130 mV dI < 700mA ; fDCDC=1MHz; tr=0.1µs; tf=0.1µs; VDDDC=1.3V Maximum output current of the IMAX SR regulator - - 1 A limited by thermal constraints and component choice SMPS regulator efficiency - 85 - % VIN=3.3V; IDDDC=300mA; fDCDC=1MHz - 75 - % VIN=5V; IDDDC=400mA; fDCDC=1.5MHz - 80 - % VIN=5V; IDDDC=400mA; fDCDC=1MHz SMPS regulator load transient response dVout/dIout -25 CC nDC CC 1) Incase of SMPS mode, It shall be ensured that the VDD output pin shall be connected on PCB level to all other VDD Input pins. 2) Incase of fSRI running with max frequency, it shall be ensured that the VDD operating range is limited to 1.235V upto 1.430V. The DCDC may be configured in this case with a nominal voltage of 1.33V±7.5%. The static accuracy and regulation parameter ranges remain also valid for this case. 3) If frequency spreading (SDFREQSPRD = 1) is activated, an additional ripple of 1% need to be considered. Data Sheet 3-385 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationPhase Locked Loop (PLL) 3.17 Phase Locked Loop (PLL) Table 3-41 PLL Parameter Symbol Values Min. Unit Typ. Max. Note / Test Condition PLL base frequency fPLLBASE CC 80 150 360 MHz VCO frequency range fVCO SR 400 - 800 MHz VCO Input frequency range fREF CC 8 - 24 MHz Modulation Amplitude MA CC 0 - 2 % Peak Period jitter DP CC -200 - 200 ps Peak Accumulated Jitter DPP CC -5 - 5 ns without modulation Total long term jitter JTOT CC - - 11.5 ns including modulation; MA ≤ 1% System frequency deviation fSYSD CC - - 0.01 % with active modulation 2 3.6 5.4 MHz 11.5 - 200 µs Modulation variation frequency fMV CC PLL lock-in time tL CC Note: The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the maximum driver and sharp edge. Note: The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz. These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the supply pins and using PCB supply and ground planes. Data Sheet 3-386 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationERAY Phase Locked Loop (ERAY_PLL) 3.18 ERAY Phase Locked Loop (ERAY_PLL) Table 3-42 PLL_ERAY Parameter Symbol Values Min. PLL Base Frequency of the ERAY PLL VCO frequency range of the ERAY PLL Unit Typ. Max. 200 320 MHz 400 - 480 MHz fPLLBASE_ERA 50 Note / Test Condition Y CC fVCO_ERAY SR VCO input frequency of the ERAY PLL fREF SR 16 - 24 MHz Accumulated_Jitter DP CC -0.5 - 0.5 ns Accumulated jitter at SYSCLK pin DPP CC -0.8 - 0.8 ns PLL lock-in time tL CC 5.6 - 200 µs Note: The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the maximum driver and sharp edge. Note: The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz. These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the supply pins and using PCB supply and ground planes. Data Sheet 3-387 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationAC Specifications 3.19 AC Specifications All AC parameters are specified for the complette operating range defined in Chapter 3.4 unless otherwise noted in colum Note / test Condition. Unless otherwise noted in the figures the timings are defined with the following guidelines: VEXT/FL EX / VD DP3 90% VSS 90% 10% 10% tr tf rise_fall Figure 3-9 Definition of rise / fall times VEXT/FL EX / VD D P3 VEXT/FL EX / VD D P3 2 VSS Timing Reference Points VEXT /FL EX / VD D P3 2 timing_reference Figure 3-10 Time Reference Point Definition Data Sheet 3-388 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationJTAG Parameters 3.20 JTAG Parameters The following parameters are applicable for communication through the JTAG debug interface. The JTAG module is fully compliant with IEEE1149.1-2000. Table 3-43 JTAG Parameter Symbol Values Unit Min. Typ. Max. Note / Test Condition TCK clock period t1 SR 25 - - ns TCK high time t2 SR 10 - - ns TCK low time t3 SR 10 - - ns TCK clock rise time t4 SR - - 4 ns TCK clock fall time t5 SR - - 4 ns TDI/TMS setup to TCK rising edge t6 SR 6.0 - - ns TDI/TMS hold after TCK rising t7 SR edge 6.0 - - ns TDO valid after TCK falling edge (propagation delay) 1) t8 CC 3.0 - - ns CL≤20pF - - 16.5 ns CL≤50pF TDO hold after TCK falling edge 1) t18 CC 2 - - ns TDO high impedance to valid from TCK falling edge 1)2) t9 CC - - 17.5 ns CL≤50pF TDO valid output to high impedance from TCK falling edge 1) t10 CC - - 17.5 ns CL≤50pF 1) The falling edge on TCK is used to generate the TDO timing. 2) The setup time for TDO is given implicitly by the TCK cycle time. t1 0.9 VD D P 0.5 VD D P t5 t2 t4 0.1 VD D P t3 MC_ JTAG_ TCK Figure 3-11 Test Clock Timing (TCK) Data Sheet 3-389 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationJTAG Parameters TCK t6 t7 t6 t7 TMS TDI t9 t8 t1 0 TDO t18 MC_JTAG Figure 3-12 JTAG Timing Data Sheet 3-390 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationDAP Parameters 3.21 DAP Parameters The following parameters are applicable for communication through the DAP debug interface. Table 3-44 DAP Parameter Symbol Values Unit Min. Typ. Max. Note / Test Condition DAP0 clock period t11 SR 6.25 - - ns DAP0 high time t12 SR 2 - - ns DAP0 low time t13 SR 2 - - ns DAP0 clock rise time t14 SR - - 1 ns f=160MHz - - 2 ns f=80MHz - - 1 ns f=160MHz - - 2 ns f=80MHz DAP0 clock fall time t15 SR DAP1 setup to DAP0 rising edge t16 SR 4 - - ns DAP1 hold after DAP0 rising edge t17 SR 2 - - ns DAP1 valid per DAP0 clock period 1) t19 CC 3 - - ns CL=20pF; f=160MHz 8 - - ns CL=20pF; f=80MHz 10 - - ns CL=50pF; f=40MHz 1) The Host has to find a suitable sampling point by analyzing the sync telegram response. t11 0.9 VD D P 0.5 VD D P t1 5 t1 2 t14 0.1 VD D P t1 3 MC_DAP0 Figure 3-13 Test Clock Timing (DAP0) DAP0 t1 6 t1 7 DAP1 MC_ DAP1_RX Figure 3-14 DAP Timing Host to Device Data Sheet 3-391 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationDAP Parameters t1 1 DAP1 t1 9 MC_ DAP1_TX Figure 3-15 DAP Timing Device to Host (DAP1 and DAP2 pins) Note: The DAP1 and DAP2 device to host timing is individual for both pins. There is no guaranteed max. signal skew. Data Sheet 3-392 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationASCLIN SPI Master Timing 3.22 ASCLIN SPI Master Timing This section defines the timings for the ASCLIN in the TC290 / TC297 / TC298 / TC299, for 5V power supply. Note: Pad asymmetry is already included in the following timings. Table 3-45 Master Mode MP+ss/MPRss output pads Parameter ASCLKO clock period Symbol 1) t50 CC Deviation from ideal duty cycle t500 CC Values Unit Note / Test Condition Min. Typ. Max. 20 - - ns CL=25pF -3 - 3 ns 0 < CL < 50pF 2) MTSR delay from ASCLKO shifting edge t51 CC -7 - 6 ns CL=25pF ASLSOn delay from the first ASCLKO edge t510 CC 5 - 35 ns CL=25pF; pad used = LPm MRST setup to ASCLKO latching edge t52 SR 30 - - ns CL=25pF MRST hold from ASCLKO latching edge t53 SR -4.5 - - ns CL=25pF 1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX. 2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. Table 3-46 Master Mode MP+sm/MPRsm output pads Parameter ASCLKO clock period Symbol 1) t50 CC Deviation from ideal duty cycle t500 CC Values Unit Note / Test Condition Min. Typ. Max. 50 - - ns CL=50pF -2 - 3+0.01 * ns 0 < CL < 200pF 2) CL MTSR delay from ASCLKO shifting edge t51 CC -10 - 10 ns CL=50pF ASLSOn delay from the first ASCLKO edge t510 CC 5 - 35 ns CL=50pF; pad used = LPm MRST setup to ASCLKO latching edge t52 SR 50 - - ns CL=50pF MRST hold from ASCLKO latching edge t53 SR -9 - - ns CL=50pF 1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX. 2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. Data Sheet 3-393 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationASCLIN SPI Master Timing Table 3-47 Master Mode MPss output pads Parameter ASCLKO clock period Symbol 1) t50 CC Deviation from ideal duty cycle t500 CC Values Unit Note / Test Condition ns CL=25pF Min. Typ. Max. 20 - - -2 - 3.5+0.035 ns * CL 0 < CL < 200pF 2) MTSR delay from ASCLKO shifting edge t51 CC -7 - 6 ns CL=25pF ASLSOn delay from the first ASCLKO edge t510 CC -7 - 6 ns CL=25pF MRST setup to ASCLKO latching edge t52 SR 31 - - ns CL=25pF, else - - ns CL=25pF, for P14.2, 33 3) P14.4, and P15.1 MRST hold from ASCLKO latching edge t53 SR -5 - - ns CL=25pF 1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX. 2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. 3) Please note that these pins didn't support the hystereses inactive feature. Table 3-48 Master Mode MPsm output pads Parameter ASCLKO clock period Symbol 1) t50 CC Deviation from ideal duty cycle t500 CC Values Unit Note / Test Condition Min. Typ. Max. 100 - - ns CL=50pF -3 - 4+0.04 * ns 0 < CL < 200pF 2) CL MTSR delay from ASCLKO shifting edge t51 CC -11 - 10 ns CL=50pF ASLSOn delay from the first ASCLKO edge t510 CC -11 - 10 ns CL=50pF MRST setup to ASCLKO latching edge t52 SR 60 - - ns CL=50pF MRST hold from ASCLKO latching edge t53 SR -10 - - ns CL=50pF 1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX. 2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. Data Sheet 3-394 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationASCLIN SPI Master Timing Table 3-49 Master Mode medium output pads Parameter ASCLKO clock period Symbol 1) t50 CC Deviation from ideal duty cycle t500 CC Values Unit Note / Test Condition Min. Typ. Max. 200 - - ns CL=50pF -8 - 4+0.06 * ns 0 < CL < 200pF 2) CL MTSR delay from ASCLKO shifting edge t51 CC -20 - 18.5 ns CL=50pF ASLSOn delay from the first ASCLKO edge t510 CC -20 - 20 ns CL=50pF MRST setup to ASCLKO latching edge t52 SR 70 - - ns CL=50pF MRST hold from ASCLKO latching edge t53 SR -10 - - ns CL=50pF 1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX. 2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. Table 3-50 Master Mode weak output pads Parameter ASCLKO clock period 1) Symbol t50 CC Deviation from ideal duty cycle t500 CC Values Min. Typ. Max. 1000 - - -30 - 2) Unit Note / Test Condition ns CL=50pF 30+0.15 * ns 0 < CL < 200pF CL MTSR delay from ASCLKO shifting edge t51 CC -75 - 75 ns CL=50pF ASLSOn delay from the first ASCLKO edge t510 CC -65 - 65 ns CL=50pF MRST setup to ASCLKO latching edge t52 SR 510 - - ns CL=50pF MRST hold from ASCLKO latching edge t53 SR -50 - - ns CL=50pF 1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX. 2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. Data Sheet 3-395 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationASCLIN SPI Master Timing t50 ASCLKO t51 t500 t51 MTSR t52 MRST t53 Data valid Data valid t510 ASLSO ASCLIN_TmgMM.vsd Figure 3-16 ASCLIN SPI Master Timing Data Sheet 3-396 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationASCLIN SPI Master Timing 3.23 ASCLIN SPI Master Timing This section defines the timings for the ASCLIN in the TC290 / TC297 / TC298 / TC299, for 3.3V power supply, Medium Performance pads, strong sharp edge (MPss), CL=25pF. Note: Pad asymmetry is already included in the following timings. Table 3-51 Master Mode MP+ss/MPRss output pads Parameter ASCLKO clock period Symbol 1) t50 CC Deviation from ideal duty cycle t500 CC Values Unit Note / Test Condition Min. Typ. Max. 40 - - ns CL=25pF -5 - 5 ns 0 < CL < 50pF 2) MTSR delay from ASCLKO shifting edge t51 CC -12 - 12 ns CL=25pF ASLSOn delay from the first ASCLKO edge t510 CC 0 - 60 ns CL=25pF; pad used = MRST setup to ASCLKO latching edge t52 SR 50 - - ns CL=25pF MRST hold from ASCLKO latching edge t53 SR -5 - - ns CL=25pF LPm 1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX. 2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. Table 3-52 Master Mode MP+sm/MPRsm output pads Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. 100 - - ns CL=50pF Deviation from ideal duty cycle t500 CC -3 - 7 ns 0 < CL < 200pF MTSR delay from ASCLKO shifting edge t51 CC -17 - 17 ns CL=50pF ASLSOn delay from the first ASCLKO edge t510 CC 0 - 60 ns CL=50pF; pad used = LPm MRST setup to ASCLKO latching edge t52 SR 85 - - ns CL=50pF MRST hold from ASCLKO latching edge t53 SR -5 - - ns CL=50pF ASCLKO clock period 1) t50 CC 2) 1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX. 2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. Data Sheet 3-397 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationASCLIN SPI Master Timing Table 3-53 Master Mode MPss output pads Parameter ASCLKO clock period Symbol 1) t50 CC Deviation from ideal duty cycle t500 CC Values Unit Note / Test Condition Min. Typ. Max. 40 - - ns CL=25pF -5 - 7+0.07 * ns 0 < CL < 200pF 2) CL MTSR delay from ASCLKO shifting edge t51 CC -12 - 12 ns CL=25pF ASLSOn delay from the first ASCLKO edge t510 CC -12 - 12 ns CL=25pF MRST setup to ASCLKO latching edge t52 SR 50 - - ns CL=25pF MRST hold from ASCLKO latching edge t53 SR -5 - - ns CL=25pF 1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX. 2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. Table 3-54 Master Mode MPsm output pads Parameter Symbol ASCLKO clock period 1) t50 CC Deviation from ideal duty cycle t500 CC Values Unit Note / Test Condition Min. Typ. Max. 200 - - ns CL=50pF -5 - 9+0.06 * ns 0 < CL < 200pF 2) CL MTSR delay from ASCLKO shifting edge t51 CC -19 - 17 ns CL=50pF ASLSOn delay from the first ASCLKO edge t510 CC -19 - 17 ns CL=50pF MRST setup to ASCLKO latching edge t52 SR 100 - - ns CL=50pF MRST hold from ASCLKO latching edge t53 SR -13 - - ns CL=50pF 1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX. 2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. Table 3-55 Master Mode medium output pads Parameter ASCLKO clock period Symbol 1) t50 CC Deviation from ideal duty cycle t500 CC 2) Data Sheet Values Unit Note / Test Condition Min. Typ. Max. 400 - - ns CL=50pF -6-0.07 * - 6+0.07 * ns 0 < CL < 200pF CL CL 3-398 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationASCLIN SPI Master Timing Table 3-55 Master Mode medium output pads (cont’d) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition MTSR delay from ASCLKO shifting edge t51 CC -33 - 25 ns CL=50pF ASLSOn delay from the first ASCLKO edge t510 CC -35 - 35 ns CL=50pF MRST setup to ASCLKO latching edge t52 SR 120 - - ns CL=50pF MRST hold from ASCLKO latching edge t53 SR -13 - - ns CL=50pF 1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX. 2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. Table 3-56 Master Mode weak output pads Parameter Symbol ASCLKO clock period 1) t50 CC Deviation from ideal duty cycle t500 CC Values Unit Note / Test Condition Min. Typ. Max. 2000 - - ns CL=50pF -110 - 150 ns 0 < CL < 200pF 2) MTSR delay from ASCLKO shifting edge t51 CC -170 - 170 ns CL=50pF ASLSOn delay from the first ASCLKO edge t510 CC -170 - 170 ns CL=50pF MRST setup to ASCLKO latching edge t52 SR 510 - - ns CL=50pF MRST hold from ASCLKO latching edge t53 SR -40 - - ns CL=50pF 1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX. 2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. Table 3-57 Master Mode A2ss output pads Parameter ASCLKO clock period Symbol 1) t50 CC Deviation from ideal duty cycle t500 CC Values Unit Note / Test Condition Min. Typ. Max. 20 - - ns CL=50pF -3 - 3 ns CL=50pF 2) MTSR delay from ASCLKO shifting edge t51 CC -4 - 4 ns CL=50pF ASLSOn delay from the first ASCLKO edge t510 CC -5 - 4 ns CL=50pF Data Sheet 3-399 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationASCLIN SPI Master Timing Table 3-57 Master Mode A2ss output pads (cont’d) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition MRST setup to ASCLKO latching edge t52 SR 17 - - ns CL=50pF MRST hold from ASCLKO latching edge t53 SR 0 - - ns CL=50pF 1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX. 2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. Table 3-58 Master Mode A2sm output pads Parameter ASCLKO clock period Symbol 1) Values t50 CC Deviation from ideal duty cycle t500 CC Unit Note / Test Condition Min. Typ. Max. 40 - - ns CL=50pF -4 - 4 ns CL=50pF 2) MTSR delay from ASCLKO shifting edge t51 CC -8 - 6 ns CL=50pF ASLSOn delay from the first ASCLKO edge t510 CC -8 - 9 ns CL=50pF MRST setup to ASCLKO latching edge t52 SR 26 - - ns CL=50pF MRST hold from ASCLKO latching edge t53 SR 0 - - ns CL=50pF 1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX. 2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. t50 ASCLKO t51 t500 t51 MTSR t52 MRST t53 Data valid Data valid t510 ASLSO ASCLIN_TmgMM.vsd Figure 3-17 ASCLIN SPI Master Timing Data Sheet 3-400 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationQSPI Timings, Master and Slave Mode 3.24 QSPI Timings, Master and Slave Mode This section defines the timings for the QSPI in the TC290 / TC297 / TC298 / TC299, for 5V pad power supply. It is assumed that SCLKO, MTSR, and SLSO pads have the same pad settings: • LVDSM output pads,LVDSH input pad, master mode, CL=25pF • Medium Performance Plus Pads (MP+): • • – strong sharp edge (MP+ss), CL=25pF – strong medium edge (MP+sm), CL=50pF – medium edge (MP+m), CL=50pF – weak edge (MP+w), CL=50pF Medium Performance Pads (MP): – strong sharp edge (MPss), CL=25pF – strong medium edge (MPsm), CL=50pF Medium and Low Performance Pads (MP/LP), the identical output strength settings: – medium edge (LP/MPm), CL=50pF – weak edge (MPw), CL=50pF Table 3-59 Master Mode Timing, LVDSM output pads for data and clock Parameter Symbol Values Min. SCLKO clock period 1) 2) Unit Note / Test Condition Typ. Max. - - ns CL=25pF t50 CC 20 Deviation from the ideal duty cycle 3) 4) t500 CC -1 - 1 ns CL=25pF MTSR delay from SCLKO shifting edge t51 CC -3 - 3 ns CL=25pF 0 - 30 ns CL=25pF; MPsm -5 - 7 ns CL=25pF; MPss -4 - 7 ns MP+ss; CL=25pF - 15 ns MP+sm; CL=25pF - - ns CL=25pF; LVDSM 5V output and LVDSH 3.3V input - - ns CL=25pF; LVDSM 5V SLSOn deviation from the ideal t510 CC programmed position -1 MRST setup to SCLK latching edge 5) t52 SR MRST hold from SCLK latching t53 SR edge 19 5) -6 5) output and LVDSH 3.3V input 1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account. 2) The capacitive load on the LVDS pins is differential, the capacitive load on the CMOS pins is single ended. 3) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX. 4) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. 5) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. Data Sheet 3-401 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationQSPI Timings, Master and Slave Mode Table 3-60 Master Mode MP+ss/MPRss output pads Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. t50 CC 20 - - ns CL=25pF Deviation from the ideal duty cycle 2) 3) t500 CC -3 - 3 ns 0 < CL < 50pF MTSR delay from SCLKO shifting edge t51 CC -7 - 6 ns CL=25pF -7 - 6 ns CL=25pF 27 4)5) - - ns CL=25pF -4.5 4)5) - - ns CL=25pF SCLKO clock period 1) SLSOn deviation from the ideal t510 CC programmed position MRST setup to SCLK latching edge 4) t52 SR MRST hold from SCLK latching t53 SR edge 1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account. 2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX. 3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. 4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. 5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL. Table 3-61 Master Mode MP+sm/MPRsm output pads for data and clock Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. t50 CC 50 - - ns CL=50pF Deviation from the ideal duty cycle 2) 3) t500 CC -2 - 3+0.01 * ns 0 < CL < 200pF MTSR delay from SCLKO shifting edge t51 CC SCLKO clock period 1) CL -10 - 10 ns CL=50pF -10 - 10 ns MP+sm; CL=50pF -13 - 1 ns MPss; CL=50pF 0 - 40 ns MP+m, MPm, LPm; CL=50pF t52 SR 50 4)5) - - ns CL=50pF MRST hold from SCLK latching t53 SR edge -9 4)5) - - ns CL=50pF SLSOn deviation from the ideal t510 CC programmed position MRST setup to SCLK latching edge 4) 1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account. 2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX. 3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. Data Sheet 3-402 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationQSPI Timings, Master and Slave Mode 4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. 5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL. Table 3-62 Master Mode timing MPss output pads for data and clock, CL=50pF Parameter Symbol Values Unit Note / Test Condition ns CL=50pF Min. Typ. Max. t50 CC 40 - - Deviation from the ideal duty cycle 2) 3) t500 CC -2 - 3.5+0.035 ns * CL 0 < CL < 200pF MTSR delay from SCLKO shifting edge t51 CC -8 - 8 ns CL=50pF -8 - 8 ns MPss; CL=50pF -1 - 15 ns MP+sm; CL=50pF 0 - 50 ns MP+m, MPm, LPm; CL=50pF t52 SR 40 4)5) - - ns CL=50pF MRST hold from SCLK latching t53 SR edge -5 4)5) - - ns CL=50pF SCLKO clock period 1) SLSOn deviation from the ideal t510 CC programmed position MRST setup to SCLK latching edge 4) 1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account. 2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX. 3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. 4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. 5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL. Table 3-63 Master Mode timing MPsm output pads Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. t50 CC 100 - - ns CL=50pF Deviation from the ideal duty cycle 2) 3) t500 CC -3 - 4+0.04 * ns 0 < CL < 200pF MTSR delay from SCLKO shifting edge t51 CC SCLKO clock period 1) CL -11 - 10 ns CL=50pF SLSOn deviation from the ideal t510 CC programmed position -11 - 10 ns CL=50pF MRST setup to SCLK latching edge 4) 60 4)5) - - ns CL=50pF -10 4)5) - - ns CL=50pF t52 SR MRST hold from SCLK latching t53 SR edge 1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account. Data Sheet 3-403 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationQSPI Timings, Master and Slave Mode 2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX. 3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. 4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. 5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL. Table 3-64 Master Mode timing MPRm/MP+m/MPm/LPm output pads Parameter Symbol Values Min. Typ. Max. t50 CC 200 - - Deviation from the ideal duty cycle 2) 3) t500 CC -10 - MTSR delay from SCLKO shifting edge t51 CC SCLKO clock period 1) Note / Test Condition ns CL=50pF 16+0.04 * ns 0 < CL < 200pF CL SLSOn deviation from the ideal t510 CC programmed position MRST setup to SCLK latching edge 4) Unit t52 SR MRST hold from SCLK latching t53 SR edge -15 - 20 ns CL=50pF -20 - 20 ns CL=50pF 70 4)5) - - ns CL=50pF -10 4)5) - - ns CL=50pF 1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account. 2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX. 3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. 4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. 5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL. Table 3-65 Master Mode Weak output pads Parameter Symbol Values Min. Typ. Max. - SCLKO clock period 1) t50 CC 1000 - Deviation from the ideal duty cycle 2) 3) t500 CC -30 - MTSR delay from SCLKO shifting edge t51 CC Unit Note / Test Condition ns CL=50pF 30+0.15 * ns 0 < CL < 200pF CL -65 - 65 ns CL=50pF -65 - 65 ns CL=50pF t52 SR 300 4)5) - - ns CL=50pF MRST hold from SCLK latching t53 SR edge -40 4)5) - - ns CL=50pF SLSOn deviation from the ideal t510 CC programmed position MRST setup to SCLK latching edge 4) 1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account. Data Sheet 3-404 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationQSPI Timings, Master and Slave Mode 2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX. 3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. 4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. 5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL. Table 3-66 Slave mode timing Parameter Symbol Values Unit Min. Typ. Max. SCLK clock period t54 SR 4 x TMAX - - ns SCLK duty cycle t55/t54 SR 40 MTSR setup to SCLK latching edge t56 SR MTSR hold from SCLK latching t57 SR edge SLSI setup to first SCLK shift edge t58 SR - 60 % 4 1) - - ns Hystheresis Inactive 5 1) - - ns Input Level AL 5 1) - - ns Input Level TTL 3.5 - - ns Hystheresis Inactive 6 - - ns Input Level AL 9 1) - - ns Input Level TTL 5 1) - - ns Hystheresis Inactive 4 1) - - ns Input Level AL 1) - - ns Input Level TTL 6 MRST delay from SCLK shift edge SLSI to valid data on MRST t59 SR t60 CC t61 SR 1) 1) 8 SLSI hold from last SCLK latching edge Note / Test Condition - - ns Only for pin 15.1, AL 3 1) - - ns Hystheresis Inactive 4 1) - - ns Input Level AL 8 1) - - ns Input Level TTL 10 - 70 ns MP+m/MPRm; CL=50pF 9 - 50 ns MP+sm/MPRsm; CL=50pF 5 - 30 ns MP+ss/MPRss; CL=25pF 40 - 300 ns MP+w/MPRw; CL=50pF 10 - 70 ns MPm/LPm; CL=50pF 10 - 55 ns MPsm; CL=50pF 5 - 30 ns MPss; CL=25pF 40 - 300 ns MPw/LPw; CL=50pF - - 5 ns 1) Except pin P15.1. Data Sheet 3-405 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationQSPI Timings, Master and Slave Mode t50 t500 0.5 VEXT/FLEX SCLK1)2) t51 SAMPLING POINT 0.5 VEXT/FLEX MTSR1) t52 t53 Data valid MRST1) Data valid t510 0.5 VEXT/FLEX SLSOn2) 1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0, ECON.B=0 (no sampling point delay). 2) t510 is the deviation from the ideal position configured with the leading delay, BACON.LPRE and BACON.LEAD > 0. QSPI_TmgMM.vsd Figure 3-18 Master Mode Timing t54 SCLKI t55 MTSR 1) MRST 1) Last latching SCLK edge First latching SCLK edge First shift SCLK edge 1) t56 0.5 VEXT/FLEX t55 t56 t57 Data valid t60 t57 Data valid t60 0.5 VEXT/FLEX t58 t59 t61 SLSI 1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0. QSPI_TmgSM.vsd Figure 3-19 Slave Mode Timing 3.25 QSPI Timings, Master and Slave Mode This section defines the timings for the QSPI in the TC290 / TC297 / TC298 / TC299, for 3.3V pad power supply. It is assumed that SCLKO, MTSR, and SLSO pads have the same pad settings: • LVDSM output pads,LVDSH input pad, master mode, CL=25pF • Medium Performance Plus Pads (MP+): • • – strong sharp edge (MP+ss), CL=25pF – strong medium edge (MP+sm), CL=50pF – medium edge (MP+m), CL=50pF – weak edge (MP+w), CL=50pF Medium Performance Pads (MP): – strong sharp edge (MPss), CL=25pF – strong medium edge (MPsm), CL=50pF Medium and Low Performance Pads (MP/LP), the identical output strength settings: Data Sheet 3-406 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationQSPI Timings, Master and Slave Mode – medium edge (LP/MPm), CL=50pF – weak edge (MPw), CL=50pF Table 3-67 Master Mode Timing, LVDSM output pads for data and clock Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. t50 CC 20 - - ns CL=25pF Deviation from the ideal duty cycle 2) 3) t500 CC -2 - 2 ns CL=25pF MTSR delay from SCLKO shifting edge t51 CC -5 - 5 ns CL=25pF -2 - 55 ns CL=25pF; MPsm -9 - 12 ns CL=25pF; MPss -7 - 12 ns MP+ss; CL=25pF -2 - 26 ns MP+sm; CL=25pF t52 SR 20 - - ns CL=25pF; LVDSM 5V output and LVDSH 3.3V input MRST hold from SCLK latching t53 SR edge -6 - - ns CL=25pF; LVDSM 5V output and LVDSH 3.3V input SCLKO clock period 1) SLSOn deviation from the ideal t510 CC programmed position MRST setup to SCLK latching edge 4) 1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account. 2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX. 3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. 4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. Table 3-68 Master Mode MP+ss/MPRss output pads Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. t50 CC 40 - - ns CL=25pF Deviation from the ideal duty cycle 2) 3) t500 CC -5 - 5 ns 0 < CL < 50pF MTSR delay from SCLKO shifting edge t51 CC -12 - 12 ns CL=25pF -12 - 12 ns CL=25pF t52 SR 50 4)5) - - ns CL=25pF MRST hold from SCLK latching t53 SR edge -5 4)5) - - ns CL=25pF SCLKO clock period 1) SLSOn deviation from the ideal t510 CC programmed position MRST setup to SCLK latching edge 4) 1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account. Data Sheet 3-407 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationQSPI Timings, Master and Slave Mode 2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX. 3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. 4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. 5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL. Table 3-69 Master Mode MP+sm/MPRsm output pads for data and clock Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. t50 CC 100 - - ns CL=50pF Deviation from the ideal duty cycle 2) 3) t500 CC -3 - 7 ns 0 < CL < 200pF MTSR delay from SCLKO shifting edge t51 CC -17 - 17 ns CL=50pF -17 - 17 ns MP+sm; CL=50pF -22 - 2 ns MPss; CL=50pF 0 - 70 ns MP+m; MPm; LPm; CL=50pF 85 4)5) - - ns CL=50pF -10 4)5) - - ns CL=50pF SCLKO clock period 1) SLSOn deviation from the ideal t510 CC programmed position MRST setup to SCLK latching edge 4) t52 SR MRST hold from SCLK latching t53 SR edge 1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account. 2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX. 3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. 4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. 5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL. Table 3-70 Master Mode timing MPss output pads Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. t50 CC 40 - - ns CL=25pF Deviation from the ideal duty cycle 2) 3) t500 CC -5 - 5+0.04 * ns CL=25pF MTSR delay from SCLKO shifting edge t51 CC SCLKO clock period 1) CL SLSOn deviation from the ideal t510 CC programmed position Data Sheet -7 - 7 ns CL=25pF -10 - 10 ns CL=25pF 3-408 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationQSPI Timings, Master and Slave Mode Table 3-70 Master Mode timing MPss output pads (cont’d) Parameter Symbol Values Min. MRST setup to SCLK latching edge 4) t52 SR MRST hold from SCLK latching t53 SR edge 50 4)5) -6 4)5) Unit Note / Test Condition Typ. Max. - - ns CL=25pF - - ns CL=25pF 1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account. 2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX. 3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. 4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. 5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL. Table 3-71 Master Mode timing MPsm output pads Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. t50 CC 200 - - ns CL=50pF Deviation from the ideal duty cycle 2) 3) t500 CC -5 - 9+0.06 * ns 0 < CL < 200pF MTSR delay from SCLKO shifting edge t51 CC SCLKO clock period 1) CL -19 - 19 ns CL=50pF SLSOn deviation from the ideal t510 CC programmed position -19 - 17 ns CL=50pF MRST setup to SCLK latching edge 4) t52 SR 100 4)5) - - ns CL=50pF MRST hold from SCLK latching t53 SR edge -13 4)5) - - ns CL=50pF 1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account. 2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX. 3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. 4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. 5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL. Table 3-72 Master Mode timing MPRm/MP+m/MPm/LPm output pads Parameter SCLKO clock period Symbol 1) Deviation from the ideal duty cycle 2) 3) Data Sheet Values Unit Note / Test Condition ns CL=50pF Min. Typ. Max. t50 CC 400 - - t500 CC -6-0.07 * - 6+0.095 * ns CL 0 < CL < 200pF CL 3-409 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationQSPI Timings, Master and Slave Mode Table 3-72 Master Mode timing MPRm/MP+m/MPm/LPm output pads (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. -25 - 33 ns CL=50pF SLSOn deviation from the ideal t510 CC programmed position -35 - 35 ns CL=50pF MRST setup to SCLK latching edge 4) t52 SR 120 4)5) - - ns CL=50pF MRST hold from SCLK latching t53 SR edge -13 4)5) - - ns CL=50pF MTSR delay from SCLKO shifting edge t51 CC 1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account. 2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX. 3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. 4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. 5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL. Table 3-73 Master Mode Weak output pads Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. t50 CC 2000 - - ns CL=50pF Deviation from the ideal duty cycle 2) 3) t500 CC -110 - 125 ns 0 < CL < 200pF MTSR delay from SCLKO shifting edge t51 CC -170 - 170 ns CL=50pF -170 - 170 ns CL=50pF t52 SR 510 4)5) - - ns CL=50pF MRST hold from SCLK latching t53 SR edge -40 4)5) - - ns CL=50pF SCLKO clock period 1) SLSOn deviation from the ideal t510 CC programmed position MRST setup to SCLK latching edge 4) 1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account. 2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX. 3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. 4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. 5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL. Data Sheet 3-410 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationQSPI Timings, Master and Slave Mode Table 3-74 Slave mode timing Parameter Symbol Values Unit Min. Typ. Max. SCLK clock period t54 SR 4 x TMAX - - ns SCLK duty cycle t55/t54 SR 40 MTSR setup to SCLK latching edge t56 SR MTSR hold from SCLK latching t57 SR edge SLSI setup to first SCLK shift edge t58 SR - 60 % 7 1) - - ns Hystheresis inactive 9 1) - - ns Input Level AL 7 1) - - ns Input Level TTL 5 1) - - ns Hystheresis inactive 11 1) - - ns Input Level AL 16 1) - - ns Input Level TTL 7 1) - - ns Hystheresis inactive 7 1) - - ns Input Level AL - - ns Input Level TTL 14 1) 11 SLSI hold from last SCLK latching edge t59 SR - - ns Only for pin P15.1, AL 1) - - ns Hystheresis inactive 7 1) - - ns Input Level AL - - ns Input Level TTL 13 - 120 ns MP+m/MPRm; CL=50pF 12.5 - 85 ns MP+sm/MPRsm; CL=50pF 5.5 - 50 ns MP+ss/MPRss; CL=25pF 70 - 500 ns MP+w/MPRw; CL=50pF 13 - 120 ns MPm/LPm; CL=50pF 13 - 100 ns MPsm; CL=50pF 6 - 52 ns MPss; CL=25pF 70 - 500 ns MPw/LPw; CL=50pF - - 9 ns 5 14 MRST delay from SCLK shift edge SLSI to valid data on MRST t60 CC t61 SR Note / Test Condition 1) 1) Except pin P15.1 Data Sheet 3-411 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationQSPI Timings, Master and Slave Mode t50 t500 0.5 VEXT/FLEX SCLK1)2) t51 SAMPLING POINT 0.5 VEXT/FLEX MTSR1) t52 MRST t53 Data valid 1) Data valid t510 SLSOn 0.5 VEXT/FLEX 2) 1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0, ECON.B=0 (no sampling point delay). 2) t510 is the deviation from the ideal position configured with the leading delay, BACON.LPRE and BACON.LEAD > 0. QSPI_TmgMM.vsd Figure 3-20 Master Mode Timing t54 First shift SCLK edge SCLKI1) t55 Last latching SCLK edge First latching SCLK edge t56 t56 t57 Data valid MTSR1) t60 MRST 0.5 VEXT/FLEX t55 t57 Data valid t60 1) 0.5 VEXT/FLEX t58 t59 t61 SLSI 1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0. QSPI_TmgSM.vsd Figure 3-21 Slave Mode Timing Data Sheet 3-412 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationMSC Timing 5 V Operation 3.26 MSC Timing 5 V Operation The following section defines the timings for 5V pad power supply. Note: Pad asymmetry is already included in the following timings. Note: Load for LVDS pads are defined as differential loads in the following timings. Table 3-75 LVDS clock/data (LVDS pads in LVDS mode) Parameter Symbol Values Min. FCLPx clock period 1) t40 CC 2 * TA 2) 3) Unit Note / Test Condition Typ. Max. - - ns LVDSM; CL=50pF Deviation from ideal duty cycle t400 CC -1 - 1 ns LVDSM; 0 < CL < 50pF SOPx output delay 6) -3 - 4 ns LVDSM; CL=50pF; option EN01 -4 - 4.5 ns LVDSM; CL=50pF; option EN01D -4 - 5 ns MP+ss/MPRss; option EN01; CL=25pF -3.5 - 7 ns MP+ss/MPRss; option EN01; CL=50pF -3 - 11 ns MP+sm/MPRsm; option EN01D; CL=50pF -2.5 - 9 ns MP+ss/MPRss; option EN23; CL=25pF -2.5 - 10 ns MP+ss/MPRss; option EN23; CL=50pF -3 - 11 ns MPss; option EN01; CL=50pF -7 - 3 ns MP+ss/MPRss; option EN01; CL=0pF -5 - 3 ns MP+sm/MPRsm; option EN01D; CL=0pF -4 - 6 ns MP+ss/MPRss; option EN23; CL=0pF -7 - 4 ns MPss; option EN01; CL=0pF t46 CC 8 * tMSC - - ns Upstream Timing t48 SR - - 200 ns Upstream Timing t49 SR - - 200 ns 4) 5) ENx output delay 6) SDI bit time SDI rise time SDI fall time 7) 7) t44 CC t45 CC Upstream Timing 1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA. 2) TA depends on the clock source selected for baud rate generation in the ABRA block of the MSC. 3) The capacitive load on the LVDS pins is differential, the capacitive load on the CMOS pins is single ended. Data Sheet 3-413 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationMSC Timing 5 V Operation 4) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted if the ABRA block is used. 5) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. 6) From FCLP rising edge. 7) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application must take care that the bit is long enough (the baud rate is low enough) so that under worst case conditions the three sampling points in the middle of the bit are not violated. Data Sheet 3-414 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationMSC Timing 5 V Operation Timing Options for t45 The wiring shown in the Figure 3-22 provides three useful timing options for t45. depending on the signals selected with the alternate output lines (ALT1 to ALT7) in the ports: • EN01 - FCLN, SON, EN0, EN1 • EN01D - FCLND, SOND, EN0, EN1 - t45 window shifted to the left • EN23 - t45 window shifted to the right - FCLN, SON, EN2, EN3 - t45 reference timing The timings corresponding to EN01, EN01D, and EN23 are defined in the LVDS mode. In order to use the EN23 timings, the application should use the EN2 and EN3 outputs of the MSC module. ALT1 FCLN ALTx LVDSM ALTy FCLP FCLND FCLN ALT7 PAD ALT1 SON ALTx LVDSM ALTy SOP SOND SON ALT7 PAD ALT1 EN0 ALTx CMOS ALTy EN1 ALT7 PAD EN2 ALT1 ALTx EN3 CMOS ALTy MSC ALT7 PAD _DoublePath_4a.vsd Figure 3-22 Timing Options for t45 Mapping B, CMOS MP Pads This timing applies for the dedicated CMOS pads, pin Mapping B: • MP strong sharp (MPss) output pads for the clock and the data signals • MP strong sharp or strong medium (MP+ss or MP+sm) output pads for enable signals Table 3-76 MPss clock/data (LVDS pads in CMOS mode, option EN01) Parameter Symbol Values Min. FCLPx clock period 1) t40 CC Deviation from ideal duty cycle t400 CC 2 * TA -2 2) 3) Note / Test Condition ns MPss; CL=50pF Typ. Max. - - - 3+0.035 * ns 4) 5) Data Sheet Unit MPss; 0 < CL < 100pF CL 3-415 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationMSC Timing 5 V Operation Table 3-76 MPss clock/data (LVDS pads in CMOS mode, option EN01) (cont’d) Parameter Symbol SOPx output delay ENx output delay 6) 6) SDI bit time SDI rise time SDI fall time 7) 7) Values Unit Note / Test Condition Min. Typ. Max. t44 CC -4 - 7 ns MPss; CL=50pF t45 CC -6 - 7 ns MP+ss/MPRss; CL=50pF -2 - 16.5 ns MP+sm/MPRsm; CL=50pF -4 - 10 ns MPss; CL=50pF 0 - 32 ns MPsm; CL=50pF; except pin P13.0 0 - 32 ns MPsm; CL=50pF; pin P13.0 5 - 45 ns MPm/MP+m/MPRm; CL=50pF -11 - 7.5 ns MP+ss/MPRss; CL=0pF -4 - 13 ns MP+sm/MPRsm; CL=0pF -10 - 7 ns MPss; CL=0pF -1 - 22 ns MPsm; CL=0pF -2 - 25 ns MP+m/MPm/MPRm; CL=0pF t46 CC 8 * tMSC - - ns Upstream Timing t48 SR - - 200 ns Upstream Timing t49 SR - - 200 ns Upstream Timing 1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA. 2) TA depends on the clock source selected for baud rate generation in the ABRA block of the MSC. 3) FCLP signal high and low can be minimum 1 * TMSC. 4) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted if the ABRA block is used. 5) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. 6) From FCLP rising edge. 7) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application must take care that the bit is long enough (the baud rate is low enough) so that under worst case conditions the three sampling points in the middle of the bit are not violated. Table 3-77 MP+sm/MPRsm clock/data Parameter FCLPx clock period Symbol 1) t40 CC Deviation from ideal duty cycle t400 CC Values Note / Test Condition Min. Typ. Max. 2 * TA - - ns MP+sm/MPRsm; CL=50pF -3 - 3+0.01 * ns MP+sm/MPRsm; 0 < CL < 200pF 2) 3) Data Sheet Unit CL 3-416 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationMSC Timing 5 V Operation Table 3-77 MP+sm/MPRsm clock/data (cont’d) Parameter Symbol SOPx output delay ENx output delay 4) 4) t44 CC t45 CC Values Min. Typ. Max. -5 - 7 5) Unit Note / Test Condition ns MP+sm; CL=50pF ns MPss; CL=50pF -13 - 2 -5 - 11 ns MP+sm/MPRsm; CL=50pF 1 - 25 ns MPsm; CL=50pF 3 - 37 ns MP+m/MPm/MPRm; CL=50pF -19 - 2 ns MPss; CL=0pF -13 - 8 ns MP+sm; CL=0pF -5 - 17 ns MPsm; CL=0pF -5 - 20 ns MPm/MP+m/MPRm; CL=0pF 1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA. 2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted if the ABRA block is used. 3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. 4) From FCLP rising edge. 5) If EN1 is configured to P13.0 the max limt is increased by 0.5ns to 2.5ns. Table 3-78 MPm/MP+m/MPRm clock/data Parameter FCLPx clock period Symbol 1) t40 CC Deviation from ideal duty cycle t400 CC Values Unit Note / Test Condition Min. Typ. Max. 2 * TA - - ns MPm/MP+m/MPRm; CL=50pF -16 - 4+0.04 * ns MPm/MP+m; 0 < CL < 200pF 2) 3) CL SOPx output delay 4) t44 CC -11 - 20 ns MPm/MP+m; CL=50pF ENx output delay 4) t45 CC -13 - 24 ns MPm/MP+m/MPRm; CL=50pF -33 - 17 ns MPm/MP+m/MPRm; CL=0pF 1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA. 2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted if the ABRA block is used. 3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. 4) From FCLP rising edge. Data Sheet 3-417 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationMSC Timing 3.3 V Operation t40 t400 FCLP t44 t44 t45 t45 SOP EN 0.5 VEXT/FLEX t48 t49 0.9 VEXT/FLEX SDI 0.1 VEXT/FLEX t46 t46 MSC_Timing_A.vsd Figure 3-23 MSC Interface Timing Note: The SOP data signal is sampled with the falling edge of FCLP in the target device. 3.27 MSC Timing 3.3 V Operation The following section defines the timings for 3.3V pad power supply. Mapping A, Combo Pads in LVDS Mode or CMOS Mode The timing applies for the LVDS pads in LVDS operating mode: • The LVDSM output pads for clock and data signals set in LVDS mode • The CMOS MP pads for enable signals, with strong driver sharp edge (MPss) or strong driver medium edge (MPsm). Table 3-79 LVDS clock/data (LVDS pads in LVDS mode) Parameter Symbol Values Min. FCLPx clock period 1) t40 CC 2 * TA 2) 3) Unit Note / Test Condition Typ. Max. - - ns LVDSM; CL=50pF Deviation from ideal duty cycle t400 CC -2 - 2 ns LVDSM; 0 < CL < 50pF SOPx output delay 6) -5 - 5 ns LVDSM; CL=50pF; option EN01 -7 - 7 ns LVDSM; CL=50pF; option EN01D 4) 5) Data Sheet t44 CC 3-418 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationMSC Timing 3.3 V Operation Table 3-79 LVDS clock/data (LVDS pads in LVDS mode) (cont’d) Parameter Symbol ENx output delay 6) SDI bit time SDI rise time SDI fall time 7) 7) Values Unit Note / Test Condition Min. Typ. Max. -7 - 9.5 ns MP+ss/MPRss; option EN01; CL=25pF -5 - 13 ns MP+ss/MPRss; option EN01; CL=50pF -5 - 26 ns MP+sm/MPRsm; option EN01D; CL=50pF -4 - 16 ns MP+ss/MPRss; option EN23; CL=25pF -4 - 17 ns MP+ss/MPRss; option EN23; CL=50pF -5 - 19 ns MPss; option EN01; CL=50pF -12 - 5.5 ns MP+ss/MPRss; option EN01; CL=0pF -9 - 11 ns MP+sm/MPRsm; option EN01D; CL=0pF -7 - 9 ns MP+ss/MPRss; option EN23; CL=0pF -12 - 7 ns MPss; option EN01; CL=0pF t46 CC 8 * tMSC - - ns Upstream Timing t48 SR - - 200 ns Upstream Timing t49 SR - - 200 ns t45 CC Upstream Timing 1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA. 2) TAmin = TMAX. When TMAX = 100 MHz,t40 = 20 ns 3) The capacitive load on the LVDS pins is differential, the capacitive load on the CMOS pins is single ended. 4) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted if the ABRA block is used. 5) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. 6) From FCLP rising edge. 7) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application must take care that the bit is long enough (the baud rate is low enough) so that under worst case conditions the three sampling points in the middle of the bit are not violated. Mapping B, CMOS MP Pads This timing applies for the dedicated CMOS pads, pin Mapping B: • MP strong sharp (MPss) output pads for the clock and the data signals • MP strong sharp or strong medium (MPss or MPsm) output pads for enable signals Data Sheet 3-419 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationMSC Timing 3.3 V Operation Table 3-80 MPss clock/data (LVDS pads in CMOS mode, option EN01) Parameter Symbol Values Min. FCLPx clock period 1) t40 CC Deviation from ideal duty cycle t400 CC 2 * TA 2) 3) -5 Unit Note / Test Condition Typ. Max. - - ns MPss; CL=50pF 7+0.07 * ns MPss; 0 < CL < 100pF - 4) 5) CL SOPx output delay 6) t44 CC -7 - 12 ns MPss; CL=50pF ENx output delay 6) t45 CC -9 - 12 ns MP+ss/MPRss; CL=50pF -4 - 26 ns MP+sm/MPRsm; CL=50pF -7 - 17 ns MPss; CL=50pF 0 - 56 ns MPsm; CL=50pF; except pin P13.0 0 - 58 ns MPsm; CL=50pF; pin P13.0 4 - 77 ns MPm/MP+m/MPRm; CL=50pF -19 - 8 ns MP+ss/MPRss; CL=0pF -7 - 19 ns MP+sm/MPRsm; CL=0pF -17 - 8 ns MPss; CL=0pF -2 - 38 ns MPsm; CL=0pF -4 - 41 ns MP+m/MPm/MPRm; CL=0pF t46 CC 8 * tMSC - - ns Upstream Timing t48 SR - - 200 ns Upstream Timing t49 SR - - 200 ns SDI bit time SDI rise time SDI fall time 7) 7) Upstream Timing 1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA. 2) TAmin = TMAX. When TMAX = 100 MHz,t40 = 20 ns 3) FCLP signal high and low can be minimum 1 * TMSC. 4) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted if the ABRA block is used. 5) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. 6) From FCLP rising edge. 7) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application must take care that the bit is long enough (the baud rate is low enough) so that under worst case conditions the three sampling points in the middle of the bit are not violated. Data Sheet 3-420 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationMSC Timing 3.3 V Operation Table 3-81 MP+sm/MPRsm clock/data Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. 2 * TA - - ns MP+sm/MPRsm; CL=50pF Deviation from ideal duty cycle t400 CC -6 - 7 ns MP+sm/MPRsm; 0 < CL < 200pF SOPx output delay 4) t44 CC -9 - 12 ns MP+sm; CL=50pF t45 CC -20 - 4 ns MPss; CL=50pF -9 - 19 ns MP+sm/MPRsm; CL=50pF 0 - 44 ns MPsm; CL=50pF 0 - 63 ns MP+m/MPm/MPRm; CL=50pF -33 - 0 ns MPss; CL=0pF -23 - 9 ns MP+sm/MPRsm; CL=0pF -9 - 28 ns MPsm; CL=0pF -9 - 31 ns FCLPx clock period 1) t40 CC 2) 3) ENx output delay 4) MPm/MP+m/MPRm; CL=0pF 1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA. 2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted if the ABRA block is used. 3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. 4) From FCLP rising edge. Table 3-82 MPm/MP+m/MPRm clock/data Parameter Symbol FCLPx clock period 1) t40 CC Deviation from ideal duty cycle t400 CC 2) 3) 4) 4) Unit Note / Test Condition Min. Typ. Max. 2 * TA - - ns MPm/MP+m/MPRm; CL=50pF -6-0.95 * - 6+0.07 * ns MPm/MP+m/MPRm; 0 < CL < 200pF CL SOPx output delay ENx output delay Values CL t44 CC -19 - 34 ns MPm/MP+m; CL=50pF t45 CC -19 - 38 ns MPm/MP+m/MPRm; CL=50pF -57 - 27 ns MPm/MP+m/MPRm; CL=0pF 1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA. 2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted if the ABRA block is used. 3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite. Data Sheet 3-421 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationMSC Timing 3.3 V Operation 4) From FCLP rising edge. t40 t400 FCLP t44 t44 t45 t45 SOP EN 0.5 VEXT/FLEX t48 t49 0.9 VEXT/FLEX SDI 0.1 VEXT/FLEX t46 t46 MSC_Timing_A.vsd Figure 3-24 MSC Interface Timing Note: The SOP data signal is sampled with the falling edge of FCLP in the target device. Data Sheet 3-422 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationEthernet Interface (ETH) Characteristics 3.28 Ethernet Interface (ETH) Characteristics 3.28.1 ETH Measurement Reference Points ETH Clock 1.4 V 1.4 V ETH I/O 2.0 V 0.8 V 2.0 V 0.8 V tR tF ETH_Testpoints.vsd Figure 3-25 ETH Measurement Reference Points Data Sheet 3-423 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationEthernet Interface (ETH) Characteristics 3.28.2 ETH Management Signal Parameters (ETH_MDC, ETH_MDIO) Table 3-83 ETH Management Signal Parameters Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition ETH_MDC period t1 CC 400 - - ns CL=25pF ETH_MDC high time t2 CC 160 - - ns CL=25pF ETH_MDC low time t3 CC 160 - - ns CL=25pF ETH_MDIO setup time (output) t4 CC 10 - - ns CL=25pF ETH_MDIO hold time (output) t5 CC 10 - - ns CL=25pF ETH_MDIO data valid (input) t6 SR 0 - 300 ns CL=25pF t1 t3 t2 ETH_MDC ETH_MDIO sourced by controller : ETH_MDC t4 ETH_MDIO (output ) t5 Valid Data ETH_MDIO sourced by PHY: ETH_MDC t6 ETH_MDIO (input ) Valid Data ETH_Timing-Mgmt.vsd Figure 3-26 ETH Management Signal Timing Data Sheet 3-424 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationEthernet Interface (ETH) Characteristics 3.28.3 ETH MII Parameters In the following, the parameters of the MII (Media Independent Interface) are described. Table 3-84 ETH MII Signal Timing Parameters Parameter Symbol Clock period t7 SR Clock high time t8 SR Values Unit Note / Test Condition Min. Typ. Max. 40 - - ns CL=25pF; baudrate=100Mbps 400 - - ns CL=25pF; baudrate=10Mbps 14 - 26 ns CL=25pF; baudrate=100Mbps 140 1) - 260 2) ns CL=25pF; baudrate=10Mbps Clock low time t9 SR 14 - 26 ns CL=25pF; baudrate=100Mbps 140 1) - 260 2) ns CL=25pF; baudrate=10Mbps Input setup time t10 SR 10 - - ns CL=25pF Input hold time t11 SR 10 - - ns CL=25pF Output valid time t12 CC 0 - 25 ns CL=25pF 1) Defined by 35% of clock period. 2) Defined by 65% of clock period. t7 t9 ETH_MII_RX_CLK ETH_MII_TX_CLK t8 ETH_MII_RX_CLK t1 0 ETH_MII_RXD[3:0] ETH_MII_RX_DV ETH_MII_RX_ER (sourced by PHY ) t1 1 Valid Data ETH_MII_TX_CLK t1 2 ETH_MII_TXD[3:0] ETH_MII_TXEN (sourced by controller ) Valid Data ETH_Timing-MII.vsd Figure 3-27 ETH MII Signal Timing Data Sheet 3-425 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationEthernet Interface (ETH) Characteristics 3.28.4 ETH RMII Parameters In the following, the parameters of the RMII (Reduced Media Independent Interface) are described. Table 3-85 ETH RMII Signal Timing Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. 20 - - ns CL=25pF; 50ppm ETH_RMII_REF_CL clock high t14 CC time 7 1) - 13 2) ns CL=25pF ETH_RMII_REF_CL clock low t15 CC time 7 1) - 13 2) ns CL=25pF ETH_RMII_REF_CL clock period t13 CC ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV, ETHRXER; setup time t16 CC 4 - - ns CL=25pF ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV, ETHRXER; hold time t17 CC 2 - - ns CL=25pF 1) Defined by 35% of clock period. 2) Defined by 65% of clock period. t1 3 t1 5 t14 ETH_RMII_REF_CL ETH_RMII_REF_CL t1 6 ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV, ETHRXER t17 Valid Data ETH_Timing-RMII .vsd Figure 3-28 ETH RMII Signal Timing Data Sheet 3-426 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationE-Ray Parameters 3.29 E-Ray Parameters The timings of this section are valid for the strong driver and either sharp edge settings of the output drivers with CL = 25 pF. For the inputs the hysteresis has to be configured to inactive. Table 3-86 Transmit Parameters Parameter Symbol Values Min. Rise time of TxEN tdCCTxENRise2 5 Fall time of TxEN Unit Note / Test Condition Typ. Max. - 9 ns CL=25pF - 9 ns CL=25pF - 9 ns 20% - 80%; CL=25pF CC tdCCTxENFall25 CC Sum of rise and fall time tdCCTxRise25+ dCCTxFall25 CC Sum of delay between TP1_FF tdCCTxEN01 CC and TP1_CC and delays derived from TP1_FFi, rising edge of TxEN - - 25 ns Sum of delay between TP1_FF tdCCTxEN10 CC and TP1_CC and delays derived from TP1_FFi, falling edge of TxEN - - 25 ns -2.45 - 2.45 ns Sum of delay between TP1_FF tdCCTxD01 and TP1_CC and delays CC derived from TP1_FFi, rising edge of TxD - - 25 ns Sum of delay between TP1_FF tdCCTxD10 CC and TP1_CC and delays derived from TP1_FFi, falling edge of TxD - - 25 ns TxD signal sum of rise and fall ttxd_sum CC time at TP1_BD - - 9 ns Asymmetry of sending ttx_asym CC CL=25pF Table 3-87 Receive Parameters Parameter Symbol Values Min. Max. - 43.0 ns CL=25pF - 44.0 ns CL=15pF 35 - 70 % 30 - 65 % tdCCTxAsymAcc -30.5 Acceptance of asymmetry at receiving part tdCCTxAsymAcc -31.5 Threshold for detecting logical high TuCCLogic1 SR Threshold for detecting logical low SR Data Sheet Note / Test Condition Typ. Acceptance of asymmetry at receiving part ept25 Unit SR ept15 SR TuCCLogic0 3-427 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationE-Ray Parameters Table 3-87 Receive Parameters (cont’d) Parameter Symbol Values Unit Min. Typ. Max. Sum of delay between TP4_CC tdCCRxD01 and TP4_FF and delays CC derived from TP4_FFi, rising edge of RxD - - 10 ns Sum of delay between TP1_CC tdCCRxD10 CC and TP1_CC and delays derived from TP4_FFi, falling edge of RxD - - 10 ns Data Sheet 3-428 Note / Test Condition V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationHSCT Parameters 3.30 HSCT Parameters Table 3-88 HSCT - Rx/Tx setup timing Parameter Symbol Values Unit Min. Typ. Max. Note / Test Condition RX o/p duty cycle DCrx CC 40 - 60 % Bias startup time tbias CC - 5 10 µs Bias distributor waking up from power down and provide stable Bias. RX startup time trxi CC - 5 - µs Wake-up RX from power down. TX startup time ttx CC - 5 - µs Wake-up TX from power down. Unit Note / Test Condition Total Budget for complete receiver including silicon, package, pins and bond wire Table 3-89 HSCT - Rx parasitics and loads Parameter Symbol Values Min. Typ. Max. Capacitance total budget Ctotal CC - 3.5 5 pF Parasitic inductance budget Htotal CC - 5 - nH Table 3-90 LVDSH - Reduced TX and RX (RED) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Output differential voltage VOD CC 150 200 285 mV Rt = 100 Ohm ±20% @2pF Output voltage high VOH CC - - 1463 mV Rt = 100 Ohm ±20% Output voltage low VOL CC 937 - - mV Rt = 100 Ohm ±20% Output offset (Common mode) VOS CC voltage 1.08 1.2 1.32 V Rt = 100 Ohm ±20% @2pF Input voltage range - - 1.6 V Absolute max = 1.6 V + (285mV/2) = 1.743 0.15 - - V Absolute min = 0.15 V (285 mV /2) = 0 V 100 mV for 55% of bit period; Note Absolute Value (Vidth - Vidthl) VI SR Input differential threshold Vidth SR -100 - 100 mV Data frequency DR CC 5 - 320 Mbps Data Sheet 3-429 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationHSCT Parameters Table 3-90 LVDSH - Reduced TX and RX (RED) (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. 90 100 110 Ohm 0 V < VI < 1.6V 80 100 120 Ohm 1.6 V < VI < 2.0V - - 2 V/ns Change in VOS between 0 and dVOS CC 1 - - 50 mV Peak to peak (including DC transients). Change in Vod between 0 and dVod CC 1 - - 50 mV Peak to peak (including DC transients) Fall time 1) tfall CC 0.26 - 1.2 ns Rt = 100 Ohm ±20% @2pF Rise time 1) trise CC 0.26 - 1.2 ns Rt = 100 Ohm ±20% @2pF Unit Note / Test Condition Receiver differential input impedance Rin CC Slew rate SRtx CC 1) Rise / fall times are defined for 10% - 90% of VOD Table 3-91 HSCT PLL Parameter Symbol Values Min. Typ. Max. PLL frequency range fPLL CC 12.5 320 320 MHz PLL input frequency fREF CC 10 - 20 MHz PLL lock-in time tLOCK CC - - 50 µs Bit Error Rate based on 10 MHz BER10 CC reference clock at Slave PLL side - - 10EXP-9 - Bit Error Rate based on Slave interface reference clock at 10 MHz Bit Error Rate based on 20 MHz BER20 CC reference clock at Slave PLL side - - 10EXP12 - Bit Error Rate based on Slave interface reference clock at 20 MHz Absolute RMS Jitter (TX out) JABS10 CC -125 - 125 ps Measured at link TX out; valid for Reference frequency at 10 MHz Absolute RMS Jitter (TX out) JABS20 CC -85 - 85 ps Measured at link TX out; valid for Reference frequency at 20 MHz Data Sheet 3-430 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationHSCT Parameters Table 3-91 HSCT PLL (cont’d) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Accumulated RMS Jitter (RX side) JACC10 CC - - 145 ps Measured at link RX input, based on 5000 measures, each 300 clock cycles; valid for Reference frequency at 10 MHz Accumulated RMS Jitter (link RX side) JACC20 CC - - 115 ps Measured at link RX input, based on 5000 measures, each 300 clock cycles; valid for Reference frequency at 20 MHz Total Jitter peak to peak TJpp CC - - 2083 ps Total Jitter as sum of deterministic jitter and random jitter Unit Note / Test Condition Table 3-92 HSCT Sysclk Parameter Symbol Values Min. Typ. Max. Frequency fSYSCLK CC 10 - 20 MHz Frequency error dfERR CC -1 - 1 % Duty Cycle DCsys CC 45 - 55 % Load impedance RLOAD CC 10 - - kOhm Load capacitance CLOAD CC - - 10 pF Integrated phase noise IPN CC - - -58 dB Data Sheet 3-431 single sideband phase noise in 10 kHz to 10 Mhz at 20 MHz SysClk V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationInter-IC (I2C) Interface Timing 3.31 Inter-IC (I2C) Interface Timing This section defines the timings for I2C in the TC290 / TC297 / TC298 / TC299. All I2C timing parameter are SR for Master Mode and CC for Slave Mode. Table 3-93 I2C Standard Mode Timing Parameter Symbol Values Unit Note / Test Condition Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Min. Typ. Max. Fall time of both SDA and SCL t1 - - 300 ns Capacitive load for each bus line - - 400 pF Bus free time between a STOP t10 and ATART condition 4.7 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Rise time of both SDA and SCL t2 - - 1000 ns Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Data hold time t3 0 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Data set-up time t4 250 - - ns Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Low period of SCL clock t5 4.7 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line High period of SCL clock t6 4 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Hold time for the (repeated) START condition t7 4 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Data Sheet Cb SR 3-432 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationInter-IC (I2C) Interface Timing Table 3-93 I2C Standard Mode Timing (cont’d) Parameter Set-up time for (repeated) START condition Symbol t8 Set-up time for STOP condition t9 Values Unit Note / Test Condition Min. Typ. Max. 4.7 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line 4 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Unit Note / Test Condition 300 ns Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Table 3-94 I2C Fast Mode Timing Parameter Symbol Values Min. Fall time of both SDA and SCL t1 Typ. 20+0.1*C - Max. b Capacitive load for each bus line Cb SR - - 400 pF Bus free time between a STOP t10 and ATART condition 1.3 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Rise time of both SDA and SCL t2 20+0.1*C - 300 ns Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line b Data hold time t3 0 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Data set-up time t4 100 - - ns Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Low period of SCL clock t5 1.3 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line High period of SCL clock t6 0.6 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Data Sheet 3-433 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationInter-IC (I2C) Interface Timing Table 3-94 I2C Fast Mode Timing (cont’d) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Hold time for the (repeated) START condition t7 0.6 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Set-up time for (repeated) START condition t8 0.6 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line Set-up time for STOP condition t9 0.6 - - µs Measured with a pullup resistor of 4.7 kohms at each of the SCL and SDA line t1 SDA t2 t4 70% 30% t1 t3 t2 t6 SCL th S t7 9 clock t5 t10 SDA t8 t7 t9 SCL th 9 clock Sr P S Figure 3-29 I2C Standard and Fast Mode Timing Data Sheet 3-434 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationEBU Timings 3.32 EBU Timings 3.32.1 BFCLKO Output Clock Timing VSS = 0 V;VDD = 1.3 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%,; CL = 35 pF Table 3-95 BFCLK0 Output Clock Timing Parameters1) Parameter Symbol Values Unit Note / Test Conditi on Min. Typ. Max. 13.332) – – ns – BFCLKO clock period tBFCLKO CC BFCLKO high time t5 CC 3 – – ns – BFCLKO low time t6 CC 3 – – ns – BFCLKO rise time t7 CC – – 3 ns – – – 3 ns – 35 50 55 % – BFCLKO fall time t8 3) BFCLKO duty cycle t5/(t5 + t6) CC DC 1) Not subject to production test, verified by design/characterization. 2) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter parameters. 3) The PLL jitter is not included in this parameter. If the BFCLKO frequency is equal to fCPU, the K divider has to be regarded. tBFCLKO BFCLKO 0.9 VDD 0.1 VDD 0.5 VDDP05 t5 t8 t6 t7 MCT04883_mod Figure 3-30 BFCLKO Output Clock Timing 3.32.2 EBU Asynchronous Timings VSS = 0 V;VDD = 1.3 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%, Class B pins; CL = 35 pF for address/data; CL = 40pF for the control lines. For each timing, the accumulated PLL jitter of the programed duration in number of clock periods must be added separately. Operating conditions apply and CL = 35 pF. Table 3-96 Common Asynchronous Timings Parameter Symbol Values Unit Min. Typ. Max. AD(31:0) output delay to ADV# t13 CC rising edge, multiplexed read / write -5.5 - 2 ns AD(31:0) output delay to ADV# t14 CC rising edge, multiplexed read / write -5.5 - 2 ns Data Sheet 3-435 Note / Test Condition V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationEBU Timings Table 3-96 Common Asynchronous Timings (cont’d) Parameter Symbol Values Unit Min. Typ. Max. Note / Test Condition Address valid to CS falling edge (deviation from programmed value) t15 CC -2 - 2 ns Address valid -> ADV falling edge (deviation from programmed value) t16 CC -2 - 2 ns ADV falling edge -> CS falling edge (deviation from programmed value) t17 CC -2 - 2 ns -0.8 - 0.8 ns edge=medium -0.8 - 0.8 ns edge=sharp Unit Note / Test Condition Pulse wdih deviation from the ta CC ideal programmed width due to pad asymmetry, rise delay - fall delay Table 3-97 Asynchronous Read Timings Parameter Symbol Values Min. Typ. Max. A(23:0) output delay to RD t0 CC rising edge, deviation from the ideal programmed value -2.5 - 2.5 ns AD(31:0) output delay to ADV# t13 CC rising edge, multiplexed read / write -2.5 - 10 ns AD(31:0) output delay to ADV# t14 CC rising edge, multiplexed read / write -2.5 - 10 ns Data input Hold from CS rising t18 CC edge -4 - - ns t19 CC 12 - - ns -2.5 - 2.5 ns Data input Setup to CS rising edge t1 CC A(23:0) output delay to RD rising edge, deviation from the ideal programmed value CS rising edge to RD rising edge, deviation from the ideal programmed value t2 CC -2 - 2.5 ns ADV rising edge to RD rising edge, deviation from the ideal programmed value t3 CC -1.5 - 4.5 ns BC rising edge to RD rising edge, deviation from the ideal programmed value t4 CC -2.5 - 2.5 ns Data Sheet 3-436 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationEBU Timings Table 3-97 Asynchronous Read Timings (cont’d) Parameter Symbol Values Unit Min. Typ. Max. WAIT input setup to RD rising edge t5 SR 12 - - ns WAIT input hold to RD rising edge t6 SR 0 - - ns Data input setup to RD rising edge t7 SR 12 - - ns Data input hold to RD rising edge t8 SR 0 - - ns -2.5 - 1.5 ns Address Phase Address Hold Phase (opt.) Command Phase Data Hold Phase Recovery Phase (opt.) ADDRC AHOLDC RDWAIT DATAC RDRECOVC 1...31 0...15 t9 CC MR / W output delay to RD# rising edge, deviation from the ideal programmed value EBU STATE Control Bitfield: Duration Limits in EBU_CLK Cycles 1...15 0...15 A[23:0] 0...15 pv + t30 pv + New Addr. Phase ADDRC 1...15 Next Addr. Valid Address CS[3:0] CSCOMB Note / Test Condition pv + t31 ta pv + t32 pv + t33 pv + ta ADV pv + ta RD/WR pv + ta pv + ta BC[3:0] t34 t35 WAIT t36 pv + AD[31:0] t14 t13 t37 Data Out Address Out MR/W pv + t38 pv + t39 pv = programmed value, TEBU_CLK * sum (correponding bitfield values) new_MuxWR_Async_10.vsd Figure 3-31 Multiplexed Read Access Data Sheet 3-437 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationEBU Timings EBU STATE Control Bitfield: Duration Limits in EBU_CLK Cycles Address Phase Address Hold Phase (opt.) ADDRC AHOLDC 1...15 0...15 A[23:0] Command Phase Data Hold Phase RDWAIT DATAC 1...31 0...15 Recovery Phase (opt.) New Addr. Phase RDRECOVC 0...15 ADDRC 1...15 Next Addr. Valid Address pv + t30 pv + CS[3:0] CSCOMB pv + t31 ta pv + t32 pv + t33 pv + ta ADV pv + ta RD/WR pv + ta pv + ta BC[3:0] t34 t35 WAIT t36 t37 AD[31:0] pv + t38 Data Out pv + t39 MR/W pv = programmed value, TEBU_CLK * sum (correponding bitfield values) new_DemuxWR_Async_10.vsd Figure 3-32 Demultiplexed Read Access Table 3-98 Asynchronous Write Timings Parameter Symbol Values Unit Min. Typ. Max. A(23:0) output delay to WR t30 CC rising edge, deviation from the ideal programmed value -2.5 - 2.5 ns t31 CC A(23:0) output delay to WR rising edge, deviation from the ideal programmed value -2.5 - 2.5 ns -2 - 2 ns CS rising edge to WR rising edge, deviation from the ideal programmed value Data Sheet t32 CC 3-438 Note / Test Condition V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationEBU Timings Table 3-98 Asynchronous Write Timings (cont’d) Parameter Symbol Values Unit Min. Typ. Max. ADV rising edge to WR rising edge, deviation from the ideal programmed value t33 CC -2.5 - 2 ns BC rising edge to WR rising edge, deviation from the ideal programmed value t34 CC -2.5 - 2 ns 12 - - ns 0 - - ns Data output delay to WR rising t37 CC edge, deviation from the ideal programmed value -5.5 - 10 ns Data output delay to WR rising t38 CC edge, deviation from the ideal programmed value -5.5 - 2 ns t39 CC MR / W output delay to WR rising edge, deviation from the ideal programmed value -2.5 - 1.5 ns WAIT input setup to WR rising t35 SR edge, deviation from the ideal programmed value WAIT input hold to WR rising edge, deviation from the ideal programmed value 3.32.3 t36 CC Note / Test Condition EBU Burst Mode Access Timing VSS = 0 V;VDD = 1.3 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%; CL = 35 pF; Table 3-99 Burst Read Timings Parameter Symbol Values Unit Min. Typ. Max. Output delay from BFCLKO rising edge t10 CC -2 - 2 ns D(31:0) Output delay from BFCLKO rising edge t10a CC -2 - 10 ns -2 - 2 ns RD and RD/WR active/inactive t12 CC after BFCLKO active edge CSx output delay from BFCLKO active edge t21 CC -2.5 - 1.5 ns ADV active/inactive after BFCLKO active edge t22 CC -2 - 2 ns BAA active/inactive after BFCLKO active edge t22a CC -2.5 - 4.5 ns Data setup to BFCLKI rising edge t23 SR 3 - - ns Data Sheet 3-439 Note / Test Condition V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationEBU Timings Table 3-99 Burst Read Timings (cont’d) Parameter Symbol Values Unit Min. Typ. Max. Data hold from BFCLKI rising edge t24 SR 0 - - ns WAIT setup (low or high) to BFCLKI rising edge t25 SR 3 - - ns WAIT hold (low or high) from BFCLKI rising edge t26 SR 0 - - ns Address Phase(s) BFCLKI BFCLKO Command Phase(s) Burst Phase(s) Burst Phase(s) Recovery Phase(s) Note / Test Condition Next Addr. Phase(s) 1) t10 t10 A[23:0] Next Addr. Burst Start Address t22 t22 t22 ADV t21 t21 t21 CS[3:0] CSCOMB t12 t12 RD RD/WR t22a t22a BAA t24 t23 D[31:0] (32-Bit) D[15:0] (16-Bit) t25 t24 t23 Data (Addr+0) Data (Addr+4) Data (Addr+0) Data (Addr+2) t26 WAIT 1) Output delays are always referenced to BCLKO. The reference clock for input characteristics depends on bit EBU_BFCON.FDBKEN. EBU_BFCON.FDBKEN = 0: BFCLKO is the input reference clock. EBU_BFCON.FDBKEN = 1: BFCLKI is the input reference clock (EBU clock feedback enabled). BurstRDWR_4.vsd Figure 3-33 EBU Burst Mode Read / Write Access Timing Data Sheet 3-440 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationEBU Timings 3.32.4 EBU Arbitration Signal Timing VSS = 0 V;VDD = 1.5 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5% ; TA = -40°C to +125°C; CL = 35 pF; Table 3-100 EBU Arbitration Timings Parameter Symbol Values Unit Min. Typ. Max. Output delay from BFCLKO rising edge t27 CC - - 4.5 ns Data setup to BFCLKO falling edge t28 SR 15 - - ns 2 - - ns Data hold from BFCLKO falling t29 SR edge Note / Test Condition BFCLKO t27 t27 HLDA Output t27 t27 BREQ Output BFCLKO t28 t28 t29 t29 HOLD Input HLDA Input EBUArb_1 Figure 3-34 EBU Arbitration Signal Timing Data Sheet 3-441 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationCIF Parameters 3.33 CIF Parameters CIF timings are valid only for temperatures up the TJ = 150°C. Table 3-101 Timings for 5V Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Pixel clock period t70 SR 10.42 - - ns 96 MHz HSYNC, VSYNC set up time t71 SR 2.5 - - ns AL input level, hysteresis bypass 2 - - ns TTL input level, hysteresis bypass 6.5 - - ns TTL input level, hysteresis on 4 - - ns AL input level, hysteresis on 2.5 - - ns AL input level, hysteresis bypass 2.5 - - ns TTL input level, hysteresis bypass 7 - - ns TTL input level, hysteresis on 4 - - ns AL input level, hysteresis on 2.5 - - ns AL input level, hysteresis bypass 2 - - ns TTL input level, hysteresis bypass 6.5 - - ns TTL input level, hysteresis on 4 - - ns AL input level, hysteresis on 2.5 - - ns AL input level, hysteresis bypass 2.5 - - ns TTL input level, hysteresis bypass 7 - - ns TTL input level, hysteresis on 4 - - ns AL input level, hysteresis on HSYNC, VSYNC hold time Pixel data set up time Pixel data hold time Data Sheet t72 SR t73 SR t74 SR 3-442 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationCIF Parameters Table 3-102 Timings for 3.3V Parameter Symbol Values Unit Min. Typ. Max. Note / Test Condition Pixel clock period t70 SR 10.42 - - ns HSYNC, VSYNC set up time t71 SR 3.5 - - ns AL input level, hysteresis bypass 4.5 - - ns AL input level, hysteresis on 9 - - ns TTL input level, hysteresis on 3 - - ns TTL input level, hysteresis bypass 4 - - ns AL input level, hysteresis bypass 5 - - ns AL input level, hysteresis on 10 - - ns TTL input level, hysteresis on 3.5 - - ns TTL input level, hysteresis bypass 3.5 - - ns AL input level, hysteresis bypass 4.5 - - ns AL input level, hysteresis on 9 - - ns TTL input level, hysteresis on 3 - - ns TTL input level, hysteresis bypass 4 - - ns AL input level, hysteresis bypass 5 - - ns AL input level, hysteresis on 10 - - ns TTL input level, hysteresis on 3.5 - - ns TTL input level, hysteresis bypass Unit Note / Test Condition HSYNC, VSYNC hold time Pixel data set up time Pixel data hold time t72 SR t73 SR t74 SR Table 3-103 Timings for 0.4V to 2.4V input signals (2.8V imager) Parameter Pixel clock period Data Sheet Symbol t70 SR Values Min. Typ. Max. 10.42 - - 3-443 ns V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationCIF Parameters Table 3-103 Timings for 0.4V to 2.4V input signals (2.8V imager) (cont’d) Parameter HSYNC, VSYNC set up time HSYNC, VSYNC hold time Pixel data set up time Pixel data hold time Symbol t71 SR t72 SR t73 SR t74 SR Values Unit Note / Test Condition Min. Typ. Max. 3 - - ns Hysteresis Bypass, 3.3V±10% 9 - - ns TTL Input Levels, 3.3V±10% 4.5 - - ns TTL Input Levels, 5V±10% 3.5 - - ns Hysteresis Bypass, 3.3V±10% 10 - - ns TTL Input Levels, 3.3V±10% 5 - - ns TTL Input Levels, 5V±10% 3 - - ns Hysteresis Bypass, 3.3V±10% 9 - - ns TTL Input Levels, 3.3V±10% 4.5 - - ns TTL Input Levels, 5V±10% 3.5 - - ns Hysteresis Bypass, 3.3V±10% 10 - - ns TTL Input Levels, 3.3V±10% 5 - - ns TTL Input Levels, 5V±10% Table 3-104 Timings for 0.4V to 2.4V input signals (2.8V imager), ±5% pad power supply Parameter Symbol Values Unit Min. Typ. Max. Note / Test Condition Pixel clock period t70 SR 10.42 - - ns HSYNC, VSYNC set up time t71 SR 3 - - ns Hysteresis Bypass, 3.3V±5% 9 - - ns TTL Input Levels, 3.3V±5% 4.5 - - ns TTL Input Levels, 5V±5% 3.5 - - ns Hysteresis Bypass, 3.3V±5% 10 - - ns TTL Input Levels, 3.3V±5% 5 - - ns TTL Input Levels, 5V±5% HSYNC, VSYNC hold time Data Sheet t72 SR 3-444 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationCIF Parameters Table 3-104 Timings for 0.4V to 2.4V input signals (2.8V imager), ±5% pad power supply (cont’d) Parameter Pixel data set up time Pixel data hold time Symbol t73 SR t74 SR Values Unit Note / Test Condition Min. Typ. Max. 3 - - ns Hysteresis Bypass, 3.3V±5% 9 - - ns TTL Input Levels, 3.3V±5% 4.5 - - ns TTL Input Levels, 5V±5% 3.5 - - ns Hysteresis Bypass, 3.3V±5% 10 - - ns TTL Input Levels, 3.3V±5% 5 - - ns TTL Input Levels, 5V±5% Unit Note / Test Condition Table 3-105 Timings for 1.8V imager, TTL input level Parameter Symbol Values Min. Typ. Max. Pixel clock period t70 SR 10.42 - - ns HSYNC, VSYNC set up time t71 SR 3 - - ns Input signal 0.1V to 1.7V 9 - - ns Input signal 0.2V to 1.6V 4.5 - - ns Input signal 0.3V to 1.5V 3.5 - - ns Input signal 0.4V to 1.4V 3.5 - - ns Input signal 0.1V to 1.7V 10 - - ns Input signal 0.2V to 1.6V 5 - - ns Input signal 0.3V to 1.5V 4 - - ns Input signal 0.4V to 1.4V 3 - - ns Input signal 0.1V to 1.7V 9 - - ns Input signal 0.2V to 1.6V 4.5 - - ns Input signal 0.3V to 1.5V 3.5 - - ns Input signal 0.4V to 1.4V HSYNC, VSYNC hold time Pixel data set up time Data Sheet t72 SR t73 SR 3-445 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationCIF Parameters Table 3-105 Timings for 1.8V imager, TTL input level (cont’d) Parameter Pixel data hold time Symbol t74 SR Values Unit Note / Test Condition Min. Typ. Max. 3.5 - - ns Input signal 0.1V to 1.7V 10 - - ns Input signal 0.2V to 1.6V 5 - - ns Input signal 0.3V to 1.5V 4 - - ns Input signal 0.4V to 1.4V Table 3-106 Timings for 1.8V imager, 3.3V±5% pad power supply, TTL input level Parameter Symbol Values Unit Min. Typ. Max. Note / Test Condition Pixel clock period t70 SR 10.42 - - ns HSYNC, VSYNC set up time t71 SR 3 - - ns Input signal 0.1V to 1.7V 9 - - ns Input signal 0.2V to 1.6V 4.5 - - ns Input signal 0.3V to 1.5V 3.5 - - ns Input signal 0.4V to 1.4V 3.5 - - ns Input signal 0.1V to 1.7V 10 - - ns Input signal 0.2V to 1.6V 5 - - ns Input signal 0.3V to 1.5V 4 - - ns Input signal 0.4V to 1.4V 3 - - ns Input signal 0.1V to 1.7V 9 - - ns Input signal 0.2V to 1.6V 4.5 - - ns Input signal 0.3V to 1.5V 3.5 - - ns Input signal 0.4V to 1.4V HSYNC, VSYNC hold time Pixel data set up time Data Sheet t72 SR t73 SR 3-446 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationCIF Parameters Table 3-106 Timings for 1.8V imager, 3.3V±5% pad power supply, TTL input level (cont’d) Parameter Pixel data hold time Data Sheet Symbol t74 SR Values Unit Note / Test Condition Min. Typ. Max. 3.5 - - ns Input signal 0.1V to 1.7V 10 - - ns Input signal 0.2V to 1.6V 5 - - ns Input signal 0.3V to 1.5V 4 - - ns Input signal 0.4V to 1.4V 3-447 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationFlash Target Parameters 3.34 Flash Target Parameters Program Flash program and erase operation is only allowed up the TJ = 150°C. Flash timing parameter are valid for fFSI = 100 MHz. Table 3-107 FLASH Parameter Symbol Program Flash Erase Time per tERP CC logical sector Program Flash Erase Time per tMERP CC Multi-Sector Command Values Unit Note / Test Condition Min. Typ. Max. - - 1 s cycle count < 1000 - 0.207 + 0.003 * (S [KByte]) / (fFSI [MHz])1) s cycle count < 1000, for sector of size S - - 1 s For consecutive logical sectors in a physical sector, cycle count < 1000 - 0.207 + 0.003 * (S [KByte]) / (fFSI [MHz])1) s For consecutive logical sector range of size S in a physical sector, cycle count < 1000 Program Flash program time per page in 5 V mode tPRP5 CC - - 50 + µs 3000/(fFSI [MHz]) 32 Byte Program Flash program time per page in 3.3 V mode tPRP3 CC - - 81 + µs 3400/(fFSI [MHz]) 32 Byte Program Flash program time per burst in 5 V mode tPRPB5 CC - - µs 125 + 9500/(fFSI [MHz]) 256 Byte Program Flash program time per burst in 3.3 V mode tPRPB3 CC - - 410 + µs 12000/(fF SI [MHz]) 256 Byte Program Flash program time for 1 MByte with burst programming in 5 V mode excluding communication tPRPB5_1MB - - 0.9 s Derived value for documentation purpose, valid for fFSI = 100MHz Program Flash program time tPRPB5_PF for complete PFlash with burst CC programming in 5 V mode excluding communication - - 7.2 s Derived value for documentation purpose, valid for fFSI = 100MHz Write Page Once adder - - 15 + 500/(fFSI [MHz]) µs Adder to Program Time when using Write Page Once Data Sheet CC tADD CC 3-448 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationFlash Target Parameters Table 3-107 FLASH (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Program Flash suspend to read tSPNDP CC latency - - 12000/(fF µs SI [MHz]) For Write Burst, Verify Erased and for multi(logical) sector erase commands Data Flash Erase Time per Sector 2) - 0.12 + 0.08/(fFSI [MHz])1) - s cycle count < 1000 - 0.57 + 0.15/(fFSI [MHz])1) 0.928 + 0.15/(fFSI [MHz]) s cycle count < 125000 - 0.12 + 0.01 * (S [KByte]) / (fFSI [MHz])1) s For consecutive logical sector range of size S, cycle count < 1000 - 0.57 + 0.019 * (S [KByte]) / (fFSI [MHz])1) s 0.928 + 0.019 * (S [KByte]) / (fFSI [MHz]) For consecutive logical sector range of size S, cycle count < 125000 Data Flash Erase Time per Multi-Sector Command 2) tERD CC tMERD CC Data Flash erase disturb limit NDFD CC - - 50 Program time data flash per page 3) tPRD CC - - 50 + µs 2500/(fFSI [MHz]) 3) 8 Byte Complete Device Flash Erase Time PFlash and DFlash 4) tER_Dev CC - - 17 Derived value for documentation purpose (excl. UCBs and HSMs), valid for fFSI = 100MHz Data Flash program time per burst 3) tPRDB CC - - 96 + µs 4400/(fFSI [MHz]) 3) Data Flash suspend to read latency tSPNDD CC - - 12000/(fF µs SI [MHz]) tFL_MarginDel - - 10 µs Program Flash Retention Time, tRET CC Sector 20 - - years Data Flash Endurance per EEPROMx sector 5) 125000 - - cycles Max. data retention time 10 years NE_HSM CC 125000 - - cycles Max. data retention time 10 years Wait time after margin change cycles s 32 Bytes CC Data Flash Endurance per HSMx sector 5) Data Sheet NE_EEP10 CC 3-449 Max. 1000 erase/program cycles V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationFlash Target Parameters Table 3-107 FLASH (cont’d) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition UCB Retention Time tRTU CC 20 - - years Max. 100 erase/program cycles per UCB, max 400 erase/program cycles in total Data Flash access delay tDF CC - - 100 ns see PMU_FCON.WSDFLA SH Data Flash ECC Delay tDFECC CC - - 20 ns see PMU_FCON.WSECD F Program Flash access delay tPF CC - - 30 ns see PMU_FCON.WSPFLA SH Program Flash ECC delay tPFECC CC - - 10 ns see PMU_FCON.WSECP F Number of erase operations on NERD0 CC DF0 over lifetime - - 750000 cycles Number of erase operations on NERD1 CC DF1 over lifetime - - 500000 cycles - - 150 °C Junction temperature limit for PFlash program/erase operations TJPFlash SR 1) All typical values were characterised, but are not tested. Typical values are safe median values at room temperature 2) Under out-of-spec conditions (e.g. over-cycling) or in case of activation of WL oriented defects, the duration of erase processes may be increased by up to 50%. 3) Time is not dependent on program mode (5V or 3.3V). 4) Using 512 KByte erase commands. 5) Only valid when a robust EEPROM emulation algorithm is used. For more details see the Users Manual. Data Sheet 3-450 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationPackage Outline Package Outline 17 ±0. 1 B 1 .7 MAX A 292 x 0.15 M C A B 0.08 M C 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 7 ±0.1 0.1 C CODE COPLANARITY INDEX MARKING (LASERED ) SEATIN G PLAN E 292 x 0.15 Y W V U T R P N M L K J HG F E D C B A 19 x 0 .8 = 1 5.2 0 .5 ±0.05 0 .8 3.35 INDEX MARKING 0.8 19 x 0.8 = 15 .2 C 0.33 MIN STANDOFF Figure 3-35 Package Outlines LF-BGA-292-6 d 0.1 2 x 25 x 1 .0 = 25 2 .15 MAX A 27 B (0.56) 2x d 0 .1 (0.95 ) +0.07 1.0 0.63 -0.13 416 x 0 .25 M C A B 0.1 M C 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 416 x 0.15 C COPLANARITY 27 CODE (LASERED ) AF AD AB Y W V U T R P N M L K J H G F E D C B A AE AC AA C INDEX MARKING SEATIN G PL ANE 0.1 C 0 ,41 MIN STAND OFF 1.0 Figure 3-36 Package Outlines PG-BGA-416-26 Data Sheet 3-451 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationPackage Outline 0.1 2 x d B 29 x 0.8 = 23.2 1.7 MAX A 25 ±0.1 2x d 0.1 0 .8 0.5 ±0.05 516 x 0 .1 5 M C A B 0.08 M C 30 0.15 CODE 25 ±0.1 COPLANARITY 2 1 AK AJ AG AE AC AA Y W V U T R P N M L K J H G F E D C B A AH AF AD AB 0.8 C INDEX MARKING SEATIN G PL ANE 0.1 C 0.8 2 9 x 0 .8 = 23 .2 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 5 16x INDEX MARKING 0 ,3 MIN (LASERED ) STAND OFF Figure 3-37 Package Outlines PG-LFBGA-516-5 You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. 3.35.1 Package Parameters Table 3-108 Thermal Characteristics of the Package Device Package RQJCT1) RQJCB1) RQJA Unit TC297 LF-BGA-292-6 3,0 4,3 15,1 K/W TC298 PG-BGA-416-26 2,9 5,4 12,8 K/W TC299 PG-LFBGA-516-5 2,8 4,3 15,1 K/W Note 1) The top and bottom thermal resistances between the case and the ambient (RTCAT, RTCAB) are to be combined with the thermal resistances between the junction and the case given above (RTJCT, RTJCB), in order to calculate the total thermal resistance between the junction and the ambient (RTJA). The thermal resistances between the case and the ambient (RTCAT, RTCAB) depend on the external system (PCB, case) characteristics, and are under user responsibility. The junction temperature can be calculated using the following equation: TJ = TA + RTJA * PD, where the RTJA is the total thermal resistance between the junction and the ambient. This total junction ambient resistance RTJA can be obtained from the upper four partial thermal resistances. Thermal resistances as measured by the ’cold plate method’ (MIL SPEC-883 Method 1012.1). 3.35.2 Data Sheet TC290 Carrier Tape 3-452 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationPackage Outline Figure 3-38 Carrier Tape Dimenions Table 3-109 TC290 Chip Dimenions Device A B T TC290 8,770 mm 9,357 mm 0,3 mm Data Sheet 3-453 V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step Electrical SpecificationQuality Declarations 3.36 Quality Declarations Table 3-110 Quality Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. - - 24500 hour ESD susceptibility according to VHBM Human Body Model (HBM) - - 2000 V ESD susceptibility of the LVDS VHBM1 pins - - 500 V ESD susceptibility according to VCDM Charged Device Model (CDM) - - 500 V for all other balls/pins; conforming to JESD22-C101-C - - 750 V for corner balls/pins; conforming to JESD22-C101-C - - 3 Operation Lifetime Moisture Sensitivity Level Data Sheet tOP MSL 3-454 Conforming to JESD22-A114-B Conforming to Jedec J-STD--020C for 240C V 1.0 2017-03 TC290 / TC297 / TC298 / TC299 BC-Step HistoryChanges from TC29xBB_v1.1 to TC29xBC_v1.0 4 History 4.1 Changes from TC29xBB_v1.1 to TC29xBC_v1.0 • • VADC – Add parameter tWU – Add parameter RMDU – Add parameter RMDD Changes in table 'Class LP 3.3V' of Standard_Pads – • Changes in table 'Class LP 5V' of Standard_Pads – • Change note of VILHLP from 'Hysteresis inactive; not available for P14.2, P14.4, and P15.1' to 'Hysteresis inactive; not available for P14.2, P14.4, P15.1, P15.10 and P15.11' ERAY – • Change note of VILHLP from 'Hysteresis inactive; not available for P14.2, P14.4, and P15.1' to 'Hysteresis inactive; not available for P14.2, P14.4, P15.1, P15.10 and P15.11' Add statement ‘The timings of this section are valid for the strong driver and either sharp edge settings of the output drivers with CL = 25 pF. For the inputs the hysteresis has to be configured to inactive.’ Package Outline – change values in table ‘TC290 Chip Dimenions’ Data Sheet 455 V 1.0 2017-03 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG